Results 151 to 160 of about 14,078 (201)
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IEEE Journal of Solid-State Circuits, 1977
VMOS technology is discussed as it applies to semiconductor memory. A 45-ns 1-kbit static RAM with a die size of 81 mil/spl times/125 mil and a cell area of 3.0 square mils is presented. The device is fabricated with the original grounded-source version of the VMOS process.
T. Rodgers +5 more
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VMOS technology is discussed as it applies to semiconductor memory. A 45-ns 1-kbit static RAM with a die size of 81 mil/spl times/125 mil and a cell area of 3.0 square mils is presented. The device is fabricated with the original grounded-source version of the VMOS process.
T. Rodgers +5 more
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1978 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, 1978
This paper will discuss the application of VMOS technology in the design of one-transistor 150 μm2memory cells using existing photolithography. The development permits fabrication of a 64K RAM in a 16-pin package.
K. Hoffmann, R. Losehand, K. Zapf
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This paper will discuss the application of VMOS technology in the design of one-transistor 150 μm2memory cells using existing photolithography. The development permits fabrication of a 64K RAM in a 16-pin package.
K. Hoffmann, R. Losehand, K. Zapf
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Quaternionic Beltrami Equations with VMO Coefficients
The Journal of Geometric Analysis, 2013zbMATH Open Web Interface contents unavailable due to conflicting licenses.
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VMO solutions of the n-laplacian
Comptes Rendus de l'Académie des Sciences - Series I - Mathematics, 1997We consider the homogeneous Dirichlet problem for the equation -div(A(x, Du))=μ in an open bounded set μ ⊂ on, where the differential operator is like the N-Laplacian and where μ is a Radon measure. We prove that such a problem admits a solution υ which is locally BMO in Ω.
Vincenzo Ferone, Nicola Fusco
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Simulation of VMOS power transistors
International Journal of Electronics, 1984Abstract The paper describes a new model for simulation of the current/voltage characteristics of VMOS power transistors. The model includes the conventional MOS theory modified by mobility reduction, non-uniform concentration distribution in the channel, and the effective resistance of the drain region. Experimental results are discussed. A comparison
Y. K. FANG +4 more
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Necessary and sufficient condition for a VMO function
Applied Mathematics and Computation, 2012zbMATH Open Web Interface contents unavailable due to conflicting licenses.
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ICM 2000. Proceedings of the 12th International Conference on Microelectronics. (IEEE Cat. No.00EX453), 2002
Partial-product reduction circuits (compressors) are of capital importance in the design of high performance parallel multipliers. This paper proposes compressor designs based on threshold gates which have been implemented as vMOS circuits. A typical block, a (4,2) compressor, is fully developed. Data for a (6,2) compressor are also provided.
J.M. Quintana +3 more
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Partial-product reduction circuits (compressors) are of capital importance in the design of high performance parallel multipliers. This paper proposes compressor designs based on threshold gates which have been implemented as vMOS circuits. A typical block, a (4,2) compressor, is fully developed. Data for a (6,2) compressor are also provided.
J.M. Quintana +3 more
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Floating output VMOS amplifier
IEEE Transactions on Circuits and Systems, 1989A differential input-differential output floating amplifier is described. The essential characteristics of the system are defined by three feature-of-merit parameters. A practical design using VMOS power transistors is also presented and the experimental measured parameters are compared to the theoretical estimates. >
J. Moncassin, M. Rabii, H. Benoit
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VMOS, UMOS technology simulation
28th International Conference on Information Technology Interfaces, 2006., 2006VMOS, UMOS ("V"-groove-metal-oxide-silicon) transistors drain and gate are formed in the groove of "V" or "U" form. Expanding channel area, therefore VMOS and UMOS structures may use in the power chips. Using VMOS, UMOS is saving 40% free space than using NMOS technology.
T. Kersys, D. Andriukaitis, R. Anilionis
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1979 International Electron Devices Meeting, 1979
This paper describes the design of a new family of VMOS power FETs exhibiting low ON resistance, high current as well as high breakdown voltage and fast switching speeds. The design which is based on a 1st-order device model, features a novel polysilicon-gate structure and a field-plated groove termination to achieve high packing density and high ...
S. Kay, C.T. Trieu, B.H. Yeh
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This paper describes the design of a new family of VMOS power FETs exhibiting low ON resistance, high current as well as high breakdown voltage and fast switching speeds. The design which is based on a 1st-order device model, features a novel polysilicon-gate structure and a field-plated groove termination to achieve high packing density and high ...
S. Kay, C.T. Trieu, B.H. Yeh
openaire +1 more source