Data Rates Assessment on L2–L3 CPU Bus and Bus between CPU and RAM in Modern CPUs
In this paper, a modern CPU architecture with several different cache levels is described, and current CPU performance limitations such as silicone physical limitations or frequency increase bounds are mentioned.
Maria S. Komar
doaj +1 more source
On chip network with increased performance for efficient wireless communication
Core systems with network transactions deployed semiconductor materials to develop wireless networks-on-chip to minimize latency with increased performance.
Suresh Ponnan, Tikkireddi Aditya Kumar
doaj +1 more source
Hardware-software implementation of the compression and transmission of seismic data [PDF]
A real-time wireless network architecture for seismic data ac-quisition system based on multi-level radio network is proposed. The sin-gle-chip programmable transceiver Si446x that allows creating the first level of the network is considered.
Murtazina Leisan Sh. +3 more
doaj +1 more source
Multi-Level Analysis of On-Chip Optical Wireless Links
Networks-on-chip are being regarded as a promising solution to meet the on-going requirement for higher and higher computation capacity. In view of future kilo-cores architectures, electrical wired connections are likely to become inefficient and ...
Franco Fuschini +9 more
doaj +1 more source
Wireless networks-on-chips: architecture, wireless channel, and devices
Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency.
Matolak, David W +5 more
openaire +2 more sources
An Emergency Monitoring System for Power Cable Tunnels Based on Mobile Wireless Sensor Network
To meet the environmental monitoring requirements of power cable tunnels for emergency cases such as communication network being missed, broken-down, or attacked, a low-cost mobile wireless senor network monitoring system was developed based on WiFi and ...
Xinqian XU +6 more
doaj +1 more source
Design and analysis of a mesh-based wireless network-on-chip [PDF]
Network-on-chip (NoC) architecture is regarded as a solution for future on-chip interconnects. However, the performance advantages of conventional NoC architectures are limited by the long latency and high power consumption due to multi-hop long distance communication among processing elements.
Wen-Hsiang Hu +2 more
openaire +3 more sources
On the Cooperative Relaying Strategies for Multi-Core Wireless Network-on-Chip
Recently, hybrid wired-wireless Network-on-Chip (WiNoC) has been proposed as a suitable communication fabric to provide scalability and satisfy high performance demands of the exascale era of modern multi/many-core System-on-Chip (SoC) design.
Quoc-Tuan Vien +3 more
doaj +1 more source
An Analytical Channel Model for Emerging Wireless Networks-on-Chip [PDF]
Recently wireless Networks-on-Chip (WiNoCs) have been proposed to overcome the scalability and performance limitations of traditional multi-hop wired NoC architectures. However, the adaptation of wireless technology for on-chip communication is still in its infancy.
Michael Opoku Agyeman +2 more
openaire +1 more source
Ray Tracing Modeling of Electromagnetic Propagation for On-Chip Wireless Optical Communications
Multi-core processors are likely to be a point of no return to meet the unending demand for increasing computational power. Nevertheless, the physical interconnection of many cores might currently represent the bottleneck toward kilo-core architectures ...
Franco Fuschini +6 more
doaj +1 more source

