Results 221 to 230 of about 34,728 (307)

Efficient 22 nm GNRFET PTLA using low power trimode technique for high speed processor. [PDF]

Sci Rep
Arora S, Tripathi SL, Wijayanto I, Saxena S.   +3 more
europepmc   +1 more source

Design and Implementation of Low-Complexity Multiple Symbol Detection Algorithm Using Hybrid Stochastic Computing in Aircraft Wireless Communications. [PDF]

Entropy (Basel)
Liu Y, Liu R, Tian K, Lu Z, Zhao L.
europepmc   +1 more source

A field-programmable gate array based on wafer-scale 2D semiconductor. [PDF]

Natl Sci Rev
Sun Q, Ao M, Dong X, Shi K, Gou S, Zhu Y, Zhang Z, Zhang J, Hu Y, Sun Z, Chen X, Wang L, Bao W, Zhou P.   +13 more
europepmc   +1 more source

Deciphering the Replication-Division Coordination in E. coli : A Unified Mathematical Framework for Systematic Model Comparison

Perrin A, Doumic M, El Karoui M, Méléard S.   +3 more
europepmc   +1 more source

Structural and functional characterisation of isolated puff adder ( B. arietans ) serine proteases

Wilkinson MC, Modahl CM, Saviola A, Tianyi F, Harrison RA, Casewell NR.   +5 more
europepmc   +1 more source

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Quaternary Quantum/Reversible Half-Adder, Full-Adder, Parallel Adder and Parallel Adder/Subtractor Circuits

International Journal of Theoretical Physics, 2019
zbMATH Open Web Interface contents unavailable due to conflicting licenses.
Majid Haghparast, Haghparast Majid
exaly   +4 more sources

Adder With Distributed Control

IEEE Transactions on Computers, 1970
An adder is described for addition of a large number of binary numbers x j , j=1, 2, ⋯, m, where x j =∑ i x ji ⋅ 2i, x ji =0, 1, i=0, 1, ⋯, n-1. The adder's algorithm has two parts: 1) the bits x ji are added independently for each binary order i:s i =∑ j x ji ≦m and the result expressed in the binary form s i =∑ k a ik , ⋅ 2k, a ik =0, 1, k=0, 1,⋯, p ...
exaly   +2 more sources

Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder

IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018
Exploiting the tradeoff between accuracy and hardware cost has a tremendous potential to improve the efficiency of integrated systems. Using this concept, numerous approximate adders have been proposed in the last ten years.
Alberto García-Ortiz, Ardalan Najafi, Ayad M Dalloo   +2 more
exaly   +2 more sources

A Low Latency Approximate Adder Design Based on Dual Sub-Adders With Error Recovery

IEEE Transactions on Emerging Topics in Computing, 2023
This paper presents a novel dual sub-adder based approximate adder that splits a precise adder into two to significantly reduce the latency. The proposed error recovery and reduction technique effectively compensates for the catastrophic accuracy ...
Hyoju Seo, Yongtae Kim
semanticscholar   +1 more source

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular Automata

IEEE Transactions on Circuits and Systems - II - Express Briefs, 2023
Quantum-dot cellular automata (QCA) is a novel nano-electronic technology. QCA has attracted wide attention due to its extremely small feature sizes at the molecular or even atomic scale and ultra-low power consumption, making it a promising candidate to
Aibin Yan, Runqi Liu, Jie Cui, Tianming Ni, P. Girard, X. Wen, Jiliang Zhang   +6 more
semanticscholar   +1 more source