Results 231 to 240 of about 34,728 (307)
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Scaling Up Multi-bit DNA Full Adder Circuits with Minimal Strand Displacement Reactions.
Journal of the American Chemical Society, 2022DNA logic circuits are based on DNA molecular programming that implements specific algorithms using dynamic reaction networks. Particularly, DNA adder circuits are key building blocks for performing digital computation.
Nuli Xie +8 more
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High-Speed Adder Design Space Exploration via Graph Neural Processes
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022Adders are the primary components in the data-path logic of a microprocessor, and thus, adder design has been always a critical issue in the very large-scale integration (VLSI) industry.
Hao Geng +5 more
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LAHAF: Low-power, area-efficient, and high-performance approximate full adder based on static CMOS
Sustainable Computing: Informatics and Systems, 2021In this article, a low power, area-efficient full adder cell designed with approximate outputs is presented. The static Complementary Metal Oxide Semiconductor (CMOS) structure is applied to design this approximate full adder energy efficient (up to 72 ...
Seyed Erfan Fatemieh +2 more
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High-Speed Hybrid-Logic Full Adder Using High-Performance 10-T XOR–XNOR Cell
IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2020Hybrid logic style is widely used to implement full adder (FA) circuits. Performance of hybrid FA in terms of delay, power, and driving capability is largely dependent on the performance of xor–xnor circuit.
Jyoti Kandpal +3 more
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Spravochnik. Inzhenernyi zhurnal, 2021
The article describes an electronic multifunctional adder for electricity metering SEM-3. The authors give the technical characteristics, the device and the principle of its operation. The presented adder is designed to monitor and account for the consumption of electricity generation and power directly from consumers, as well as in automated ...
A. N. Brysin +3 more
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The article describes an electronic multifunctional adder for electricity metering SEM-3. The authors give the technical characteristics, the device and the principle of its operation. The presented adder is designed to monitor and account for the consumption of electricity generation and power directly from consumers, as well as in automated ...
A. N. Brysin +3 more
openaire +1 more source
A review on all-optical logic adder: Heading towards next-generation processor
, 2021In this paper few literatures on all-optical adders, reported approximately in last fifteen years, have been reviewed. Being the key element of arithmetic and logic unit (ALU), adder has attracted stirring attention of the researchers.
Kamanashis Goswami +2 more
semanticscholar +1 more source
A low-power dynamic ternary full adder using carbon nanotube field-effect transistors
, 2021Ternary logic uses fewer interconnects than binary logic, and smaller voltage swings are required for the same information transfer. Carbon Nanotube transistors (CNFETs) have many advantages over Metal Oxide Semiconductor transistors (MOSFETs), such as ...
Farzin Mahboob Sardroudi +2 more
semanticscholar +1 more source
IEEE Transactions on Computers, 1996
Summary: A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder.
L. Dadda, V. Piuri
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Summary: A well-known scheme for obtaining high throughput adders is a pipeline in which each stage contains an array of half-adders performing a carry-save addition. This paper shows that other schemes can be designed, based on the idea of pipelining a serial-input adder or a ripple-carry adder.
L. Dadda, V. Piuri
openaire +1 more source
Block-Based Carry Speculative Approximate Adder for Energy-Efficient Applications
IEEE Transactions on Circuits and Systems - II - Express Briefs, 2020In this brief, a low energy consumption block-based carry speculative approximate adder is proposed. Its structure is based on partitioning the adder into some non-overlapped summation blocks whose structures may be selected from both the carry propagate
Farhad Ebrahimi-Azandaryani +4 more
semanticscholar +1 more source
Design and Analysis of 8-bit ripple Carry Adder using nine Transistor Full Adder
2021 7th International Conference on Advanced Computing and Communication Systems (ICACCS), 2021This paper uses a nine-transistor full adder model to design an eight-bit ripple carry adder for less power consumption. The conventional full adder design consists of 28 transistors which constitute high power consumption.
G. Padmini +5 more
semanticscholar +1 more source