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IRE Transactions on Electronic Computers, 1962
A large, extremely fast digital adder with sum selection and multiple-radix carry is described. Boolean expressions for the operation are included. The amount of hardware and the logical delay for a 100-bit ripple-carry adder and a carry-select adder are compared.
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A large, extremely fast digital adder with sum selection and multiple-radix carry is described. Boolean expressions for the operation are included. The amount of hardware and the logical delay for a 100-bit ripple-carry adder and a carry-select adder are compared.
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Hybrid Logical Effort for Hybrid Logic Style Full Adders in Multistage Structures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2019One of the critical issues in the advancement of very large scale of integration circuit design is the estimation of timing behavior of the arithmetic circuits.
hareesh-reddy basireddy +2 more
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High Performance Error Tolerant Adders for Image Processing Applications
Journal of the Institution of Electronics and Telecommunication Engineers, 2018In this paper, we proposed High Performance Error Tolerant Adders (HPETA) which have an efficient design and quality metrics for inexact computing applications.
R. Jothin, C. Vasanthanayaki
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Energy-efficient approximate adders for DSP applications
Analog Integrated Circuits and Signal Processing, 2021Anubothula Tirupathireddy +2 more
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APPAs: fast and efficient approximate parallel prefix adders and multipliers
Journal of SupercomputingBahram Rashidi
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Area-time-power tradeoffs in parallel adders
IEEE Transactions on Circuits and Systems Part 2: Express Briefs, 1996R M Owens, C Nagendra
exaly