Low Error Efficient Approximate Adders for FPGAs [PDF]
IEEE Access, 2021 In this paper, we propose a methodology for designing low error efficient approximate adders for FPGAs. The proposed methodology utilizes FPGA resources efficiently to reduce the error of approximate adders.
Waqar Ahmad +2 more
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A Novel Approximate Adder Design Using Error Reduced Carry Prediction and Constant Truncation
IEEE Access, 2021 This paper proposes a novel approximate adder that exploits an error-reduced carry prediction and constant truncation with error reduction schemes. The proposed adder design techniques significantly improve overall computation accuracy while providing ...
Yongtae Kim, Hyoju Seo, Hyelin Seok
exaly +3 more sources
Design of Approximate Adder With Reconfigurable Accuracy
IEEE AccessArithmetic circuits such as adders are fundamental components in implementing image processing applications. Since these applications are error-tolerant, the adders can be approximated to improve their PDP (Power-Delay-Product) metric while maintaining ...
Aalelai Vendhan +2 more
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Area efficient approximate multiplier based on novel 4:2 compressors and error correction logic [PDF]
Scientific ReportsMultipliers are key components in arithmetic circuits, with their design having a significant impact on overall system performance. Approximate computing techniques seek to improve energy efficiency, processing speed and better use of hardware resources,
Krishna Prashanth P, Nithish Kumar V
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Efficient design and implementation of approximate FA, FS, and FA/S circuits for nanocomputing in QCA. [PDF]
PLoS ONERecently, there has been a lot of research in Quantum Cellular Automata (QCA) technology because it promises low power consumption, low complexity, low latency, and compact space.
Saeid Seyedi, Hatam Abdoli
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Novel approximate adaptive carry lookahead adder for error resilient applications with generic method for error analysis [PDF]
Scientific ReportsThe paper presents a novel architecture of approximate adder and a novel generic error analysis method. The proposed architecture judiciously make use of time axis based parallelism of components to improve delay and simultaneously improvement in error ...
Viraj Joshi, Pravin Mane
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Approximate Full-Adders: A Comprehensive Analysis
IEEE AccessApproximate computing is a technique that sacrifices the accuracy of the result for an advantage in terms of power, area, and speed. It is useful for error-tolerant applications such as image and video processing. Many approximate arithmetic circuits can
Ettore Napoli +3 more
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A Novel High-Speed and Low-PDP Approximate Full Adder Cell for Image Blending
Mathematics, 2023 This paper presents a new and high-performance inaccurate Full Adder Cell utilizing the Carbon Nanotube Field Effect Transistor (CNFET) technology.
Saeid Gorgin, , Mehdi Hosseinzadeh
exaly +3 more sources
Reducing T-count and T-depth in approximate quantum Fourier transform circuits [PDF]
Scientific ReportsThe quantum Fourier transform (QFT) is a fundamental component in various quantum algorithms, including Shor’s factoring algorithm and the Harrow-Hassidim-Lloyd (HHL) algorithm for solving systems of linear equations.
Byeongyong Park, Doyeol Ahn
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Hardware Optimized and Error Reduced Approximate Adder
Electronics (Switzerland), 2019 This paper presents a new hardware optimized and error reduced approximate adder (HOERAA), which is suitable for field programmable gate array (FPGA)- and application specific integrated circuit (ASIC)-based implementations. In this work, we consider a FPGA-based implementation using Xilinx Vivado 2018.3, targeting an Artix-7 FPGA.
P Balasubramanian +2 more
exaly +4 more sources