Results 11 to 20 of about 693 (252)
Approximate adder design with simplified lower-part approximation
IEICE Electronics Express, 2020 Yongtae Kim, Hyoju Seo, Jungwon Lee
exaly +3 more sources
Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs
Sensors, 2021 Adders are constituted as the fundamental blocks of arithmetic circuits and are considered important for computation devices. Approximate computing has become a popular and developing area, promising to provide energy-efficient circuits with low power ...
Avireni Bhargav, Phat Huynh
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Privacy leakages in approximate adders [PDF]
2017 IEEE International Symposium on Circuits and Systems (ISCAS), 2017 Approximate computing has recently emerged as a promising method to meet the low power requirements of digital designs. The erroneous outputs produced in approximate computing can be partially a function of each chip's process variation. We show that, in such schemes, the erroneous outputs produced on each chip instance can reveal the identity of the ...
Shahrzad Keshavarz, Daniel E. Holcomb
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IMAGIN: Library of IMPLY and MAGIC NOR-Based Approximate Adders for In-Memory Computing
IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2022 In-memory computing (IMC) has attracted significant interest in recent years as it aims to bridge the memory bottleneck in the Von Neumann architectures. IMC also improves the energy efficiency in these architectures.
Chandan Kumar Jha +3 more
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Approximate Adder with Reduced Error [PDF]
2019 IEEE 31st International Conference on Microelectronics (MIEL), 2019 A new approximate adder is proposed, which is suitable for FPGA-and ASIC-based implementations. Here, we consider an Artix-7 FPGA for the implementations using Vivado 2018.3. For 32-bit addition, the proposed approximate adder with an 8-bit least significant inaccurate sub-adder reports an improvement in the maximum frequency by 7.7% compared to the ...
Balasubramanian, Padmanabhan +2 more
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IEEE Access, 2021 This article presents a novel approximate adder that is design-optimized and has optimized error metrics. Optimization in design translates into optimization of the design parameters such as delay, power, and area/resources, and optimization of the error
Padmanabhan Balasubramanian +3 more
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Hardware Efficient Approximate Adder Design [PDF]
TENCON 2018 - 2018 IEEE Region 10 Conference, 2018 This paper presents a new approximate adder architecture which when implemented on an FPGA consumes fewer logic resources compared to accurate adders of similar size and can achieve higher or comparable operating frequencies. For 32-bit addition, our approximate adder achieves a 25% reduction in the number of LUTs utilized compared to the accurate ...
Balasubramanian, Padmanabhan +1 more
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DAEM: A Data- and Application-Aware Error Analysis Methodology for Approximate Adders
Information, 2023 Approximate adders are some of the fundamental arithmetic operators that are being employed in error-resilient applications, to achieve performance/energy/area gains.
Muhammad Abdullah Hanif +2 more
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Memories - Materials, Devices, Circuits and Systems, 2022 IoT uses wireless sensor networks (WSN) to deploy many sensors to track environmental and physical parameters. The WSN measurements are frequently contaminated and altered by noise.
Charles Rajesh Kumar J. +2 more
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Design of Low-Power Approximate Logarithmic Multipliers with Improved Accuracy [PDF]
Journal of Applied Research in Electrical Engineering, 2023 Approximate computing is considered a promising way to design high-performance and low-power arithmetic units recently. This paper proposes an energy-efficient logarithmic multiplier for error-tolerant applications.
Mojtaba Arab Nezhad, Ali Mahani
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