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Thermodynamic Limits of Fault-Tolerant Quantum Computing Beyond the Weak-Coupling, Quasistatic Regime. [PDF]
Entropy (Basel)Guha Majumdar M.
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Polarization-controlled chiral transport. [PDF]
Light Sci ApplZhu H, Wang J, Alù A, Chen L.
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An Improved GAS Algorithm. [PDF]
Entropy (Basel)Wang Z, He Y, Luan T, Long Y.
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Quantum computing applications in drug discovery. [PDF]
Brief BioinformLi J, Wei L, Tong HHY, Zou Q.
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Non-Thermal Food Processing Technologies and Polyphenols: LC-MS Evidence for Stability, Transformation, and Functionality. [PDF]
FoodsLi C, Xie C, Ghafoor K, Suleria HAR.
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Low power adiabatic logic based on FinFETs
Science China Information Sciences, 2014With the aggressive scaling of device technology, the leakage power has become the main part of power consumption, which seriously reduces the energy recovery efficiency of adiabatic logic. In this paper, a novel low-power adiabatic logic based on FinFET devices has been proposed.
Xiaoxin Cui, Nan Liao, Kaisheng Ma
exaly +2 more sources
Proceedings of IEEE Custom Integrated Circuits Conference - CICC '94, 1995
With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-Adiabatic Dynamic Logic (ADL)-that is the result of combining adiabatic theory with ...
Alex G. Dickinson, John S. Denker
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With adiabatic techniques for capacitor charging, theory suggests that it should be possible to build gates with arbitrarily small energy dissipation. In practice the complexity of adiabatic approaches has made them impractical. We describe a new CMOS logic family-Adiabatic Dynamic Logic (ADL)-that is the result of combining adiabatic theory with ...
Alex G. Dickinson, John S. Denker
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Clock Aligned Input Adiabatic Logic
Microelectronics Journal, 2021Abstract Adiabatic logic families employing four phase trapezoidal power clock, require T/4 phase shift between the input and clock and therefore require insertion of additional buffer for synchronization. This manuscript proposes Clock Aligned Input Adiabatic Logic (CAIAL) which eliminates the T/4 phase shift requirement between the clock and inputs,
Aditya S. Kumar +2 more
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2007 IEEE International Symposium on Circuits and Systems, 2007
Power clock generators (PCGs) are the prevalent overhead for the adiabatic systems and mutilate all the low-power advantage from the adiabatic logic part by consuming a large portion of the total power in the clock generation circuitry (Arsalan and Shams, 2005).
Muhammad Arsalan, Maitham Shams
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Power clock generators (PCGs) are the prevalent overhead for the adiabatic systems and mutilate all the low-power advantage from the adiabatic logic part by consuming a large portion of the total power in the clock generation circuitry (Arsalan and Shams, 2005).
Muhammad Arsalan, Maitham Shams
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Scaling trends in adiabatic logic
Proceedings of the 2nd conference on Computing frontiers, 2005Adiabatic circuits which are able to dissipate less energy than the fundamental limit of static CMOS are promising candidates for low-power circuits in the frequency range in which signals are digitally processed. This paper shows the main sources of the energy dissipation in adiabatic circuits.
Jürgen Fischer +2 more
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