Results 131 to 140 of about 952 (175)

Arithmetic Logic Unit Using Diode Free Adiabatic Logic and Selection Unit for Adiabatic Logic Family

2018 5th International Conference on Signal Processing and Integrated Networks (SPIN), 2018
Reduction in energy dissipation is an active area of research. Systems which consume power require the deployment of expensive cooling systems. In this paper a 1-bit ALU circuit has been designed in diode free adiabatic logic methodology which has much superior performance than CMOS circuits considering power dissipation and power delay product. An apt
Vasudev Grover, Vishwas Gosain, Neeta Pandey, Kirti Gupta   +3 more
openaire   +1 more source

Adiabatic-CMOS/CMOS-adiabatic logic interface circuit

International Journal of Electronics, 2000
This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it
K. T. Lau, W. Y. Wang, K. W. Ng
openaire   +1 more source

An adiabatic quaternary logic circuit

International Journal of Electronics, 1997
Multiple-valued logic has been proposed as a means for reducing the power, improving the speed, and increasing the packing density of VLSI circuits. Lowenergy (adiabatic) logic circuits have also been proposed to reduce energy consumption of VLSI logic functions. Instead of the conventional DC power supply, these adiabatic logic circuits use ‘AC’ power
K. W. CURRENT, C. L. MCDONALD
openaire   +1 more source

Adiabatic implementation of reversible logic

48th Midwest Symposium on Circuits and Systems, 2005., 2005
Reversible circuits are applicable to nanotechnology, quantum and optical computing, as well as to reducing power in CMOS implementations. In adiabatic circuits, current is restricted to flow across devices with low voltage drop and the energy stored on their capacitors is recycled. We first introduce a new reversible gate capable to realize functions {
A. Khazamipour, K. Radecka
openaire   +1 more source

Handshaking quasi-adiabatic logic

2009 52nd IEEE International Midwest Symposium on Circuits and Systems, 2009
This paper proposes a novel handshaking quasi-adiabatic logic (HQAL) circuit, which combines the advantages of adiabatic logics with those of asynchronous circuits. A HQAL circuit is composed of adiabatic logic blocks and the handshake control chain (HCC).
Meng-Chou Chang, Chia-Chang Tsai
openaire   +1 more source

Implementation of reversible logic gates using adiabatic logic

2015 IEEE Power, Communication and Information Technology Conference (PCITC), 2015
In recent years, VLSI designers are more concerned about power minimization of digital circuits and in this field the reversible logic design has emerged as one of the powerful tool due to its low power consumption feature. Adiabatic logic is also an attractive solution for energy minimization.
Yatin Gupta, Trailokya Nath Sasamal
openaire   +1 more source

Adiabatic Logic Circuits

2009
This chapter contains sections titled: Zig-Zag Path to Understanding A Low-Power Multiphase Circuit Technique Asymptotically Zero Energy Split-Level Charge Recovery Logic Low Power Digital Systems Based on Adiabatic Switching Principles Adiabatic Dynamic ...
openaire   +1 more source

Efficient power clock generation for adiabatic logic

ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2002
Practical issues in the design of power clock generators needed by adiabatic logic circuits are explained. Synchronous and asynchronous power clock generators are designed for an 8-bit adiabatic carry look-ahead adder and the more energy efficient circuit for the power clock generation is determined to be the 2N synchronous power clock generator that ...
Hamid Mahmoodi-Meimand, Ali Afzali-Kusha
openaire   +1 more source

Low power Adiabatic Logic based on 2PC2AL

2017 IEEE International Conference on IC Design and Technology (ICICDT), 2017
This paper presents a new adiabatic circuit based on the 2-Phase Clocked CMOS Adiabatic Logic (2PC2AL). By adding two logic switches between the power supply and charging-discharging transistor, it can prevent the floating of the nodes and avoid unnecessary energy loss.
Mei Han, Yasuhiro Takahashi, Toshikazu Sekine   +2 more
openaire   +1 more source

Fundamentals of Adiabatic Logic

2012
The charging process in Adiabatic Logic is the key to understand the saving potential of those ultra-low-power circuits. A figure of merit based on the energy dissipated within one operation is presented, that allows opposing Adiabatic Logic and static CMOS.
openaire   +1 more source