Results 271 to 280 of about 4,797 (308)

A fast reliability-aware approach for analogue integrated circuits based on Pareto fronts

2013 IEEE 11th International New Circuits and Systems Conference (NEWCAS), 2013
Reliability becomes a critical challenge in analogue integrated circuits (ICs) design in deep sub-micron region. In order to manufacture ICs with high quality, methodology and analysis must include reliability consideration in design loop. In this paper, we propose a new statistical reliability-aware approach to evaluate circuit performance under ...
Hao Cai 0001, Hervé Petit, Jean-François Naviner   +2 more
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Parametric yield enhancement of analogue integrated circuits: a new approach

1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1991
Two algorithms for the parametric yield enhancement of analog ICs have been developed. Those parameters which are under the designer's control are geometric in nature and are collectively represented by a point in geometric space (G-space) whose axes are typically device widths. The aim of the yield enhancement algorithm is to move the point in G-space
M. Singha, R. Spence
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Statistical modelling of Idd testing efficiency of analogue integrated circuits

Proceedings of ISSE'95 - International Symposium on Signals, Systems and Electronics, 2002
The paper describes a new implementation of a testing-algorithm model for analogue circuits. It is based on the possibilities of HSPICE and MATLAB to manage a whole test simulation including the simulation of faulty or fault free circuits as well as their post-processing. The approach takes into account the tolerance deviations of the parameters.
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Realistic faults mapping scheme for the fault simulation of integrated analogue CMOS circuits

Proceedings International Test Conference 1996. Test and Design Validity, 2002
A new fault modelling scheme for integrated analogue CMOS circuits referred to as Local Layout Realistic Fault Mapping is introduced. It is aimed at realistic fault assumptions prior to the final layout by investigating typical "local" layout structures of analogue designs.
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Memristor Circuits as Linear-Gradient Systems and Discrete Analogues Preserving a First Integral

IEEE Transactions on Circuits and Systems I: Regular Papers
The paper considers a wide class of nonlinear circuits with an ideal memristor, capacitors, inductors and current or voltage sources. A fundamental dynamical property is that each memristor circuit in this class admits a first integral (invariant of motion or preserved quantity), i.e., a function which is constant along the solutions.
Mauro Di Marco, Mauro Forti, Luca Pancioni, Giacomo Innocenti, Alberto Tesi   +4 more
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An intelligent design system for analogue integrated circuit

Proceedings of the European Design Automation Conference, 1990., EDAC., 2002
Georges G. E. Gielen, Koen Swings, Willy M. C. Sansen   +2 more
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An approach to design-for-testability automation of analogue integrated circuits using OBIST strategy

2016 5th Mediterranean Conference on Embedded Computing (MECO), 2016
© 2016 IEEE.This paper is mainly focused on the task of design-for-testability (DFT) automation with emphasis on OBIST strategy for analog integrated circuits. The design procedures according to DFT flow are proposed. Three possible structural solutions for reconfiguration of original circuit into oscillator are considered.
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Analogue integrated circuit technology

2003
George Clayton, Steve Winder
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Interactive symbolic distortion analysis of analogue integrated circuits

Proceedings of the European Conference on Design Automation., 2002
Piet Wambacq, Georges G. E. Gielen, Willy Sansen   +2 more
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Analogue Integrated Circuits

Electronics and Power, 1986
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