Results 181 to 190 of about 146,240 (250)
Architecture Design of a Convolutional Neural Network Accelerator for Heterogeneous Computing Based on a Fused Systolic Array. [PDF]
Zong Y, Ma Z, Ren J, Cao Y, Li M, Liu B.
europepmc +1 more source
Efficient FPGA implementation of polar codes-based information reconciliation for quantum key distribution. [PDF]
Liao L +10 more
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Inter-Channel Error Calibration Method for Real-Time DBF-SAR System Based on FPGA. [PDF]
Meng Y +7 more
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Efficient computation and design of high speed double precision Vedic multiplier architecture. [PDF]
Kumar AS +5 more
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Development of Compact Electronics for QEPAS Sensors. [PDF]
Zecchino V +5 more
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Design of high-performance, accurate, and approximate Dadda-tree multipliers for image processing applications. [PDF]
Rather AA +3 more
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Efficient optimization accelerator framework for multi-state spin Ising problems. [PDF]
Garg C, Salahuddin S.
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