Results 181 to 190 of about 146,240 (250)

Architecture Design of a Convolutional Neural Network Accelerator for Heterogeneous Computing Based on a Fused Systolic Array. [PDF]

Sensors (Basel)
Zong Y, Ma Z, Ren J, Cao Y, Li M, Liu B.
europepmc   +1 more source

Efficient FPGA implementation of polar codes-based information reconciliation for quantum key distribution. [PDF]

Sci Rep
Liao L, Wu X, Chen Y, Fan X, Tian Z, Huang J, Mu T, Guo J, Liu M, Liu B, Sun S.   +10 more
europepmc   +1 more source

Inter-Channel Error Calibration Method for Real-Time DBF-SAR System Based on FPGA. [PDF]

Sensors (Basel)
Meng Y, Qiu J, Wang P, Liu Y, Yang Z, Wei Y, Cheng X, Feng Y.   +7 more
europepmc   +1 more source

Efficient computation and design of high speed double precision Vedic multiplier architecture. [PDF]

Sci Rep
Kumar AS, Sahitya G, Kusuma R, Krishna MS, Reddy BNK, Tripathi SL.   +5 more
europepmc   +1 more source

Development of Compact Electronics for QEPAS Sensors. [PDF]

Sensors (Basel)
Zecchino V, Lombardi L, Marzocca C, Patimisco P, Sampaolo A, Spagnolo VL.   +5 more
europepmc   +1 more source

Design of high-performance, accurate, and approximate Dadda-tree multipliers for image processing applications. [PDF]

Sci Rep
Rather AA, Khurshid B, Banday SA, Algarni AA.   +3 more
europepmc   +1 more source

Efficient optimization accelerator framework for multi-state spin Ising problems. [PDF]

Nat Commun
Garg C, Salahuddin S.
europepmc   +1 more source