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FPGA-Assisted Deterministic Routing for FPGAs

2019 IEEE International Parallel and Distributed Processing Symposium Workshops (IPDPSW), 2019
FPGA routing is one of the most time-consuming steps of FPGA compilation, often preventing fast edit-compiletest cycles in prototyping and development. There have been attempts to accelerate FPGA routing using algorithmic improvements, multi-core or multi-CPU platforms. Instead, we propose porting FPGA routing to a CPU+FPGA platform.
Korolija, Dario, Stojilovic, Mirjana
openaire   +2 more sources

DSSS with FPGA

2007 IEEE 15th Signal Processing and Communications Applications, 2007
In this paper, we present the implementation of Direct Sequence Spread Spectrum (DSSS) on Field Programmable Gate Array (FPGA) using one of the hardware definition languages ,Very High Speed Circuit Hardware Description Language (VHDL).AIgorithms are implemented on 3s100 evg100-4 device, belonging to Xlinx FPGA family.These systems are used in mobile ...
Ilker, Ethem Okan   +2 more
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FPGA Architecture: Principles and Progression

IEEE Circuits and Systems Magazine, 2021
Since their inception more than thirty years ago, field-programmable gate arrays (FPGAs) have been widely used to implement a myriad of applications from different domains. As a result of their low-level hardware reconfigurability, FPGAs have much faster
Andrew Boutros, V. Betz
semanticscholar   +1 more source

FPGA-NHAP: A General FPGA-Based Neuromorphic Hardware Acceleration Platform With High Speed and Low Power

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2022
Spiking neural network (SNN) can process discrete spikes and offers a high degree of real-time performance and excellent energy efficiency ratio. However, most current neuromorphic hardware platforms lack efficient driven algorithms and only support a ...
Yijun Liu   +3 more
semanticscholar   +1 more source

FPGA

Proceedings of the 2009 ACM SIGMOD International Conference on Management of data, 2009
While there seems to be a general agreement that next years' systems will include many processing cores, it is often overlooked that these systems will also include an increasing number of different cores (we already see dedicated units for graphics or network processing).
René Müller 0001, Jens Teubner
openaire   +1 more source

FTRANS: energy-efficient acceleration of transformers using FPGA

International Symposium on Low Power Electronics and Design, 2020
In natural language processing (NLP), the "Transformer" architecture was proposed as the first transduction model replying entirely on self-attention mechanisms without using sequence-aligned recurrent neural networks (RNNs) or convolution, and it ...
Bingbing Li   +9 more
semanticscholar   +1 more source

HSC-FPGA

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019
The HSC-FPGA offers an intriguing feasible architecture for the next generation of configurable fabrics, which allows embracing the advantages of both CMOS and beyond-CMOS technologies without requiring significant modification to the routing structure, programming paradigms, and synthesis tool-chain of the commercial FPGAs.
Ramtin Zand, Ronald F. DeMara
openaire   +1 more source

Gigaop DSP on FPGA

2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221), 2002
DSP algorithms such as automated target recognition and SONAR beamforming are a good match for FPGA technology due to their regular structure, available parallelism, pipeline-ability, and modest data word sizes. FPGA implementations of these applications outperformed their DSP and microprocessor counterparts by factors ranging from 10× on up with an ...
Brad L. Hutchings, Brent E. Nelson
openaire   +1 more source

TRACER-fpga: a router for RAM-based FPGA's

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 1995
We describe a routing method for the design of a class of RAM-based field programmable gate arrays (FPGA). We model the interconnect resources as a graph. A routing solution is represented as a set of disjoint trees, each connecting all terminals of a net, on the graph. An expansion router is used for connecting a net.
Ching-Dong Chen   +3 more
openaire   +1 more source

FPGA-Based Sensorless Speed Control of PMSM Using Enhanced Performance Controller Based on the Reduced-Order EKF

IEEE Journal of Emerging and Selected Topics in Power Electronics, 2021
In permanent magnet synchronous motor (PMSM) speed control, the PI closed-loop control model for current does exist. Although the standard PI closed-loop control has the basic tracking capability from the PMSM control system, however, the expected ...
Hong Yang   +3 more
semanticscholar   +1 more source

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