Results 221 to 230 of about 453,183 (277)

FPGA Viruses

1999
Programmable logic is widely used, for applications ranging from field-upgradeable subsystems to advanced uses such as reconfigurable computing platforms which are modifiable at run-time. Users can thus implement algorithms which are largely executed by a general-purpose CPU, but may be selectively accelerated with special purpose hardware.
Hadžić, Ilija, Udani, Sanjay, Smith, Jonathan M   +2 more
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FPGAs in the Cloud

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017
Ever greater amounts of computing and storage are happening remotely in the cloud, and it is estimated that spending on public cloud services will grow by over 19%/year to $140B in 2019. Besides commodity processors, network and storage infrastructure, the end of clock frequency scaling in traditional processors has meant that application-specific ...
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Hybrid FPGA Architecture

Fourth International ACM Symposium on Field-Programmable Gate Arrays, 1996
This paper proposes a new field-programmable architecture that is a combination of two existing technologies: Field Programmable Gate Arrays (FPGAs) based on LookUp Tables (LUTs), and Complex Programmable Logic Devices based on PALs/PLAs. The methodology used for development of the new architecture, called Hybrid FPGA, is based on analysis of a large ...
Alireza Kaviani, Stephen Brown 0003
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The FPGA challenge

Proceedings. 1998 28th IEEE International Symposium on Multiple- Valued Logic (Cat. No.98CB36138), 2002
Examines some key issues in the development of field-programmable gate arrays (FPGAs). Design factors that determine the performance and effectiveness of these devices are discussed. The main emphasis is on the structure of logic blocks and interconnection resources. Potential areas for application of multiple-valued logic techniques are considered.
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fpga-ToPSS

Proceedings of the 5th ACM international conference on Distributed event-based system, 2011
In this demo, we present fpga-ToPSS (a member of Toronto Publish/Subscribe System Family), an efficient event processing platform for high-frequency and low-latency algorithmic trading. Our event processing platform is built over reconfigurable hardware---FPGAs---to achieve line-rate processing. Furthermore, our event processing engine supports Boolean
Mohammad Sadoghi, Harsh Singh, Hans-Arno Jacobsen   +2 more
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Preemptive multitasking on FPGAs

Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871), 2002
In exploring the efficacy of reconfigurable computing, one of the dimensions is the possibility for multitasking on an FPGA-based processor. Conventional computers and operating systems have demonstrated the many advantages of sharing computational hardware by several tasks over time.
Levinson, Lorne, Männer, Reinhard, Sessler, Matthias, Simmler, Harald   +3 more
openaire   +2 more sources

FPGA programming for the masses

Communications of the ACM, 2013
The programmability of FPGAs must improve if they are to be part of mainstream computing.
David F. Bacon, Rodric M. Rabbah, Sunil Shukla   +2 more
openaire   +1 more source

A flexible FPGA-to-FPGA communication system

2016 18th International Conference on Advanced Communication Technology (ICACT), 2016
In high-performance computing systems, each computing node communicates via a high-speed serial bus to ensure sufficient data transfer bandwidth. However, each computing node of different bus protocols is very difficult to communicate directly, which is not conducive to the extensibility of HPC (High performance computing) clusters.
An Wu, Xi Jin, Xueliang Du, ShuaiZhi Guo
openaire   +1 more source

A digital architecture for support vector machines: theory, algorithm, and FPGA implementation

IEEE Trans. Neural Networks, 2003
In this paper, we propose a digital architecture for support vector machine (SVM) learning and discuss its implementation on a field programmable gate array (FPGA).
D. Anguita, A. Boni, S. Ridella
semanticscholar   +1 more source

OPU: An FPGA-Based Overlay Processor for Convolutional Neural Networks

IEEE Transactions on Very Large Scale Integration (vlsi) Systems, 2020
Field-programmable gate array (FPGA) provides rich parallel computing resources with high energy efficiency, making it ideal for deep convolutional neural network (CNN) acceleration.
Yunxuan Yu, Chen Wu, Tiandong Zhao, Kun Wang, Lei He   +4 more
semanticscholar   +1 more source