Results 201 to 210 of about 428 (244)
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2016 IEEE 24th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2016
In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency.
Andreas Becher +4 more
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In this paper, we propose a novel approximate adder structure for LUT-based FPGA technology. Compared with a full featured accurate carry-ripple adder, the longest path is significantly shortened which enables the clocking with an increased clock frequency.
Andreas Becher +4 more
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Analysis and Design of Adders for Approximate Computing
ACM Transactions on Embedded Computing Systems, 2017The concept of approximate computing, that is, to sacrifice computation quality for computation efforts, has recently emerged as a promising design approach. Over the past decade, several research works have explored approximate computing at both the software level and hardware level of abstraction with encouraging results. At the hardware
Sunil Dutt +2 more
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Approximate Adder Tree Synthesis for FPGAs
2019 International Conference on ReConFigurable Computing and FPGAs (ReConFig), 2019Compressor trees can be used as parts of larger arithmetic circuits in application-specific accelerators. Machine learning and other application domains that are amenable to approximate arithmetic can leverage approximate accelerators constructed from approximate arithmetic components.
Sina Boroumand, Philip Brisk
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Linear-time error calculation for approximate adders
Computers and Electrical Engineering, 2021Abstract Design space exploration of Low Power Approximate Adders (LPAAs) has become significant as it successfully trades acceptable amounts of accuracy for the power, area, and delay improvements. Evaluating all potential choices in the vast design space over given application requirements and suitable error metrics makes application-oriented ...
Morteza Rezaalipour, Masoud Dehyadegari
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Design and evaluation of approximate adders
2020 IEEE 14th International Conference on Anti-counterfeiting, Security, and Identification (ASID), 2020Approximate computing technique has become a new paradigm for circuit and system performance improvement. This paper proposes an approximate adder design method by re-encoding the adder outputs using genetic algorithm under the average error (AE) constraint and evaluating the area of the approximate adder with ABC tool. Based on this method, the 2-bit,
Xue Wang +3 more
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Energy-Efficient Design of Approximated Full Adders
2020 27th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2020This work analyses a set of approximate full adder circuits in 7nm FinFET device technology in order to identify how energy-efficient these designs are for different voltage operation points. The behavior in a specific environment with voltage scaling is compared to conventional exact adders.
Pedro Aquino Silva, Cristina Meinhardt
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Exploring the use of parallel prefix adder topologies into approximate adder circuits
2017 24th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2017Approximate adders are usually composed of two parts, i.e., the imprecise (approximate) part, which is a set of the least significant bits, and a precise part, with the remaining most significant bits. Previous works have exploited only the ripple carry adder (RCA) in the precise part of approximate adders.
Morgana Macedo +4 more
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A comparative survey of approximate adders
2016 26th International Conference Radioelektronika (RADIOELEKTRONIKA), 2016The gap between capabilities of CMOS technology scaling and requirements of future application workloads is increasing rapidly. There are several promising design approaches that jointly can reduce this gap significantly. Approximate computing is one of them and in recent years, has attracted the strongest attention of the scientific community ...
Sunil Dutt +2 more
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Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2018Exploiting the tradeoff between accuracy and hardware cost has a tremendous potential to improve the efficiency of integrated systems. Using this concept, numerous approximate adders have been proposed in the last ten years. Although conceptually different, all previous architectures have been obtained with an ad hoc and nonsystematic methodology ...
Ayad Dalloo +2 more
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SEDA - Single Exact Dual Approximate Adders for Approximate Processors
Proceedings of the 56th Annual Design Automation Conference 2019, 2019Approximate computing has gained a lot of popularity due to its energy benefits in a variety of error-tolerant applications. In this paper we are proposing an adder which can perform n-bit single exact addition or dual approximate addition (SEDA), and is suitable for processors.
Chandan Kumar Jha 0001, Joycee Mekie
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