Results 11 to 20 of about 8,261 (169)
Energies, 2020 Smart Grids (SGs) can be successfully supported by Wireless Sensor Networks (WSNs), especially through these consisting of intelligent sensors, which are able to efficiently process the still growing amount of data.
Marta Kolasa
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A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines
Technologies, 2020 The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has ...
Vasileios Leon +5 more
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Advances in Medical Education and Practice, 2022 Joshua Owolabi Anatomy Department, Division of Basic Medical Sciences, University of Global Health Equity, Butaro, RwandaCorrespondence: Joshua Owolabi, Email jowolabi@ughe.orgAbstract: The ASIC [adaptation, standardisation, integration and compliance ...
Owolabi J
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Zhejiang Daxue xuebao. Lixue ban, 2010 针对智能水表控制芯片与LCD驱动芯片之间信号编码不一致并且转换复杂的问题,提出了一种ZY886B型液晶模块的接口电路.为提高转换速率、节省开销,设计的关键部分采用基于快速二-十进制转换算法的电路,该算法与其它二-十进制转换算法相比具有转换速率和面积上的优势.所设计LCD接口采用Verilog HDL描述,在Modelsim 6.0 SE版本上进行仿真和验证,在Design Compiler综合平台上进行优化综合.结果显示接口满足ZY886B的工作时序,最大时钟频率超过250 MHz,动态功耗小于1 mW.
ZHAOFeng(赵峰), XIAYin-shui(夏银水)
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ASICs and cardiovascular homeostasis [PDF]
Neuropharmacology, 2015 In this review we address primarily the role of ASICs in determining sensory signals from arterial baroreceptors, peripheral chemoreceptors, and cardiopulmonary and somatic afferents. Alterations in these sensory signals during acute cardiovascular stresses result in changes in sympathetic and parasympathetic activities that restore cardiovascular ...
François M, Abboud +1 more
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IEEE Access, 2020 In this article, accurate physical and SPICE model of wafer-level monolayer molybdenum disulfide (MoS2) device are developed to guide the devices and circuits design, which is the foundation of high-performance analog chip design.
Shunli Ma +11 more
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System-Level Leakage Power Estimation Model for ASIC Designs
Advances in Electrical and Electronic Engineering, 2018 With advances in CMOS- technology and sub-micron process, leakage power dissipation has become a critical design metric. To incorporate more functions, designs are getting complex, thereby increases leakage power dissipation.
Abhishek Narayan Tripathi +1 more
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Performance test of front-end ASIC chip CSNS_VASD developed for China Spallation Neutron Source
He jishuBackgroundThe neutron scintillator detector is one of the main detectors for China Spallation Neutron Source (CSNS). High detection efficiency is the design goal of the second-generation neutron scintillator detector, which is in process of development ...
YANG Hao +10 more
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Multifunctional computing-in-memory SRAM cells based on two-surface-channel MoS2 transistors
iScience, 2021 Summary: Driven by technologies such as machine learning, artificial intelligence, and internet of things, the energy efficiency and throughput limitations of the von Neumann architecture are becoming more and more serious.
Fan Wang +7 more
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ASIC Clouds: Specializing the Datacenter
2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA), 2016 GPU and FPGA-based clouds have already demonstrated the promise of accelerating computing-intensive workloads with greatly improved power and performance. In this paper, we examine the design of ASIC Clouds, which are purpose-built datacenters comprised of large arrays of ASIC accelerators, whose purpose is to optimize the total cost ...
Magaki, Ikuo +3 more
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