Results 21 to 30 of about 115,723 (273)

VMM3a, an ASIC for tracking detectors

Journal of Physics: Conference Series, 2020
The VMM3a is a System on Chip (SoC) custom Application Specific Integrated Circuit (ASIC)1. It is the production version which will be used as the front ASIC for both Micromegas and sTGC detectors of the ATLAS Muon New Small Wheels upgrade at CERN.
G. Iakovidis
semanticscholar   +1 more source

Bilirubin enhances the activity of ASIC channels to exacerbate neurotoxicity in neonatal hyperbilirubinemia in mice

Science Translational Medicine, 2020
Neonatal hyperbilirubinemia aggravates acidosis-dependent long-term brain injury. Targeting acidity in jaundice Neonatal hyperbilirubinemia, also called jaundice, is a pediatric condition caused by high bilirubin levels.
Ke Lai, Xing-Lei Song, Haosong Shi, Xin Qi, Chun-yan Li, Jia Fang, Fan Wang, Oleksandr P Maximyuk, O. Krishtal, Tian-Le Xu, Xiao-Yan Li, Kun Ni, Wan-Peng Li, Hai-Bo Shi, Lu-Yang Wang, S. Yin   +15 more
semanticscholar   +1 more source

Evaluation of the PETsys TOFPET2 ASIC in multi-channel coincidence experiments [PDF]

EJNMMI Physics, 2019
Background Aiming to measure the difference in arrival times of two coincident γ -photons with an accuracy in the order of 200ps, time-of-flight positron emission tomography systems commonly employ silicon photomultipliers (SiPMs) and high-resolution ...
V. Nadig, D. Schug, B. Weissler, V. Schulz   +3 more
semanticscholar   +1 more source

Characterisation of Medipix3 Silicon Detectors in a Charged-Particle Beam [PDF]

, 2015
While designed primarily for X-ray imaging applications, the Medipix3 ASIC can also be used for charged-particle tracking. In this work, results from a beam test at the CERN SPS with irradiated and non-irradiated sensors are presented and shown to be in ...
Akiba, K., Alozy, J., Aoude, R., Buytaert, J., Collins, P., Dumps, R., Gallas, A., Hombach, C., Hynds, D., John, M., Leflat, A., Li, Y., Plackett, R., Pérez, P. Rodríguez, Reid, M. M., Schindler, H., Sierra, C. Vázquez, Suárez, A. Dosil, Trigo, E. Pérez, Tsopelas, P., van Beuzekom, M., Velthuis, J. J., Wysokiński, M.   +22 more
core   +3 more sources

The Development of ASIC Type GSR Sensor Driven by GHz Pulse Current

Italian National Conference on Sensors, 2020
The GigaHertz spin rotation (GSR) effect was observed through the excitement of Giga Hertz (GHz) pulse current flowing through amorphous wire. The GSR sensor that was developed provides excellent features that enhanced magnetic sensitivity and sine ...
Y. Honkura, S. Honkura
semanticscholar   +1 more source

An Energy-Efficient, Parallel Neighborhood and Adaptation Functions for Hardware Implemented Self-Organizing Maps Applied in Smart Grid

Energies, 2020
Smart Grids (SGs) can be successfully supported by Wireless Sensor Networks (WSNs), especially through these consisting of intelligent sensors, which are able to efficiently process the still growing amount of data.
Marta Kolasa
doaj   +1 more source

A TensorFlow Extension Framework for Optimized Generation of Hardware CNN Inference Engines

Technologies, 2020
The workloads of Convolutional Neural Networks (CNNs) exhibit a streaming nature that makes them attractive for reconfigurable architectures such as the Field-Programmable Gate Arrays (FPGAs), while their increased need for low-power and speed has ...
Vasileios Leon, Spyridon Mouselinos, Konstantina Koliogeorgi, Sotirios Xydis, Dimitrios Soudris, Kiamal Pekmestzi   +5 more
doaj   +1 more source

PARISROC, a Photomultiplier Array Integrated Read Out Chip [PDF]

, 2009
PARISROC is a complete read out chip, in AMS SiGe 0.35 !m technology, for photomultipliers array. It allows triggerless acquisition for next generation neutrino experiments and it belongs to an R&D program funded by the French national agency for ...
Berni, M. El, Campagne, J. E., De La Taille, C., Di Lorenzo, S. Conforti, Dulucq, F., Martin-Chassard, G., Wei, W.   +6 more
core   +5 more sources

LUT-Lock: A Novel LUT-Based Logic Obfuscation for FPGA-Bitstream and ASIC-Hardware Protection [PDF]

IEEE Computer Society Annual Symposium on VLSI, 2018
In this work, we propose LUT-Lock, a novel Look-Up-Table-based netlist obfuscation algorithm, for protecting the intellectual property that is mapped to an FPGA bitstream or an ASIC netlist. We, first, illustrate the effectiveness of several key features
Hadi Mardani Kamali, K. Z. Azar, K. Gaj, H. Homayoun, Avesta Sasan   +4 more
semanticscholar   +1 more source

ASIC Framework Simplified and Operationalised – An Operational Matrix for Optimising the Use of Technologies and Innovations in Medical Education

Advances in Medical Education and Practice, 2022
Joshua Owolabi Anatomy Department, Division of Basic Medical Sciences, University of Global Health Equity, Butaro, RwandaCorrespondence: Joshua Owolabi, Email jowolabi@ughe.orgAbstract: The ASIC [adaptation, standardisation, integration and compliance ...
Owolabi J
doaj