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Validation of ASIP Architecture Description
2008 Fifth IEEE International Symposium on Embedded Computing, 2008Validation is one of the most complex and expensive tasks in current Application Specific Instruction Set Processors (ASIP) design process. Many existing approaches employ a multiple-level approach to efficiently design and verify ASIP design. This paper presents a novel extended timed Petri net model called HDPN-Hardware Design based-on Petri Net to ...
Yan-yan Gao, Xi Li, Jie Yu
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ASIPs for artificial neural networks
2011 6th IEEE International Symposium on Applied Computational Intelligence and Informatics (SACI), 2011Customized application-specific processors called ASIPs are becoming commonplace in contemporary embedded system designs. Neural networks are an interesting application for which an ASIP can be tailored to increase performance, lower power consumption and/or increase throughput.
Daniel Shapiro +4 more
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Dual-pipeline heterogeneous ASIP design
Proceedings of the 2nd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis - CODES+ISSS '04, 2004In this paper we demonstrate the feasibility of a dual pipeline Application Specific Instruction Set Processor. We take a C program and create a target instruction set by compiling to a basic instruction set, from which some instructions are merged, while others discarded.
Swarnalatha Radhakrishnan +2 more
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Processor Models for ASIP Design
2002The ASIP design methodology presented within the scope of this book is based on machine descriptions in the LISA language. Starting from one sole description of the target architecture the complete processor design can be addressed — architecture exploration, architecture implementation, software tools for application design, and system integration and
Andreas Hoffmann +2 more
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Dynamically Adapted Low Power ASIPs
2009New generations of embedded devices, following the trend found in personal computers, are becoming computationally powerful. A current embedded scenario presents a large amount of complex and heterogeneous functionalities, which have been forcing designers to create novel solutions to increase the performance of embedded processors while, at the same ...
Mateus B. Rutzig +2 more
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Symbolic binding for clustered VLIW ASIPs
Proceedings 2000 International Conference on Computer Design, 2002The paper proposes a symbolic framework to address the binding problem for embedded VLIW ASIPs. Alternative objective functions as well as trade-offs relevant to the binding phase of code generation for embedded processors are presented and discussed.
S. Pillai, M. Jacome
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Exploring storage organization in ASIP synthesis
Euromicro Symposium on Digital System Design, 2003. Proceedings., 2003Performance estimation which drives the design space exploration is usually done by simulation. With increasing dimensions of the design space, simulator based approaches become too time consuming. In the domain of application specific instruction set processors (ASIP), this problem can be solved by scheduler based approaches, which are much faster ...
M.K. Jain, M. Balakrishnan, A. Kumar
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China Communications, 2015
Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets.
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Baseband ASIP designs for handsets are discussed based on the author's R&D backgrounds. Algorithms for 4G, 3G, and WLAN are analyzed and selected for implementation based on the trade off of cost and performance with power consumption in mind. A SDR ASIP baseband system architecture is proposed for 4G and 3G mobile handsets.
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Evaluation of ASIPs Design with LISATek
2008This paper evaluates an ASIP design methodology based on the extension of an existing instruction set and architecture described with LISA 2.0 language. The objective is to accelerate the ASIPs design process by using partially predefined, configurable RISC-like embedded processor cores that can be quickly tuned to given applications by means of ISE ...
Rashid Muhammad +2 more
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