Results 151 to 160 of about 1,077 (202)

Issues in the design of analog BiCMOS integrated circuits

1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96, 2002
In this paper we will discuss the trade-offs between cost and performance with respect to bipolar devices in analog circuit design. We will show that for most analog designs a low cost BiCMOS process will suffice and provide the designer with significant benefits to justify the added cost. We will show which modifications should be made to a given CMOS
F. Larsen, M. Ismail
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BiCMOS Digital Integrated Circuits

1993
In this chapter, we introduce a variety of digital BiCMOS circuit structures such as the totem-pole BiCMOS gate and the merged MOS/bipolar current mode circuits. This chapter starts with a brief comparison between MOS and bipolar devices in terms of their current drive capabilities. The advantage of using bipolar devices for the totem-pole structure is
Sherif H. K. Embabi, Abdellatif Bellaouar, Mohamed I. Elmasry   +2 more
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A methodology for worst-case design of BiCMOS integrated circuits

Proceedings of the 1988 Bipolar Circuits and Technology Meeting,, 2003
A corners methodology for BiCMOS is derived using CMOS corners as the basis. Five corners for CMOS are proposed. Coupled to the four axis corners are two bipolar corners per CMOS corner. This implies that for BiCMOS there are a total of nine possible transistor corners that are superimposed on temperature, voltage, and resistor variation.
A.R. Alvarez, J. Arreola, S.Y. Pai, K.N. Ratnakumar   +3 more
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Design Methodology for BiCMOS Millimeter-Wave Integrated Circuits

2018
The design of millimeter-wave circuits involves understanding and dealing with new challenges, which make every design step crucial for a successful design. For instance, the high frequency of operation makes almost every layout connection behave as a transmission line, and therefore, they need to be adequately modeled and sized.
David del Rio, Ainhoa Rezola, Juan F. Sevillano, Igone Velez, Roc Berenguer   +4 more
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SiGe BiCMOS integrated circuits for high-speed serial communication links

IBM Journal of Research and Development, 2003
Considerable progress has been made in integrating multi-Gb/s functions into silicon chips for data- and telecommunication applications. This paper reviews the key requirements for implementing such functions in monolithic form and describes their implementation in the IBM SiGe BiCMOS technology.
Daniel J. Friedman, Mounir Meghelli, Benjamin D. Parker, Jungwook Yang, Herschel A. Ainspan, Alexander V. Rylyakov, Young Hoon Kwark, Mark B. Ritter, Lei Shan, Steven J. Zier, Michael Sorna, Mehmet Soyuer   +11 more
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Fast Prototyping for BiCMOS Analog Integrated Circuits Design

1998
At University Bordeaux 1, analog integrated circuit electronics teaching adresses students from ‘IUP Genie Electrique et Informatique Industrielle’ second and third year, from Licence and Maitrise Electronique, Electrotechnique et Automatique (EEA) and from DESS Microelectronique (from Bachelors to Masters of Science).
J. Tomas, E. Ragbi, P. Fouillat, J. P. Dom   +3 more
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Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors, 2002
In this paper, we describe how we have exploited the advantages of various methods for device recognition and modeling in a layout-to-circuit extractor, called Space. Hence, we have obtained a program that, for different technologies, can quickly translate a large layout into an equivalent network.
Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs   +2 more
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STAIC: a synthesis tool for CMOS and BiCMOS analog integrated circuits

1991 IEEE International Symposium on Circuits and Systems (ISCAS), 1991
STAIC is an interactive design tool that synthesizes CMOS and BiCMOS analog integrated circuits which conform to specified performance constraints. STAIC features an input modeling language for entering hierarchical circuit descriptions and a symbolic/numeric solver unit for dynamic integration of analytical model equations across hierarchical ...
J.P. Harvey, M.I. Elmasry, B. Leung
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Integrated BiCMOS process and circuit development using SPR

Proceedings of 15th IEEE/CHMT International Electronic Manufacturing Technology Symposium, 2002
An integrated process development environment is described. Geometry information for process simulation is taken automatically from a commercial layout tool, and process step information exists in a high-level language databank. Doping information can be read by a device simulator, permitting SPICE (simulation program with IC emphasis)-like circuit ...
R. Ryter, R. Zingg, C. Hegarty, W. Fichtner, E. Doering   +4 more
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A 700 Mb/s BiCMOS read channel integrated circuit

2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177), 2002
A read channel IC achieves >1.5 dB SNR improvement over a 32/34 rate EPRML read channel at 2.8 user bit density. The 0.18 /spl mu/m BiCMOS chip operates up to 700 Mb/s with 1.8 W read mode power using 3.3 V analog and 1.8 V digital power supplies. The die area is 9.64 mm/sup 2/.
S. Altekar, H. Chan, null Jenn-Gang Chern, R. Contreras, null Leo Fang, null Hairong Gao, R. Gee, P. Ha, K. Hsieh, null Yenyu Hsieh, D. Hsu, null Xi Huang, H. Kim, H. Kimura, P. Lai, I. Mohammed, L. Moser, null Shih-Ming Shih, M. Sugawara, Y. Tamura, H. Thapar, null Yong Wang, null Danfeng Xu, null Jiazhi Yang, A. Yeung   +24 more
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