Results 111 to 120 of about 1,893,473 (266)
Four-Bit Parallel Multiplier based on Digital Circuit Design
This paper presents an investigation into a four-bit parallel multiplier based on an enhanced digital circuit design. The advent of computers and digital electronic systems has led to a significant increase in the importance of multiplication operations in a wide range of applications.In this paper, the circuit is designed using the Logisim, and the ...
openaire +1 more source
A Combined 16-Bit Binary And Dual Galois Field Multiplier
Galois field arithmetic is commonly used in Reed-Solomon encoding and decoding. This paper presents the design of a combined 16-bit binary and dual Galois field (GF) multiplier.
Michael J. Schulte +2 more
core
Contact‐Free Human‐Machine Interfaces via Printed Thermopile Infrared Arrays
Can a printed sheet locate and sense a fingertip without being touched? Fully printed, flexible thermoelectric arrays convert the infrared from a hovering finger directly into voltage, with no external power. Aerosol‐jet‐printed silver mirrors partially shield each pixel, creating a local temperature gradient.
Zirui Wang +9 more
wiley +1 more source
A chip‐level VCMA‐MTJ array is demonstrated for stochastic neural‐network computing. Combined with a tail‐truncation strategy to compensate for device‐to‐device variations, it establishes a hardware–software co‐design approach for scalable probabilistic computing.
Jiachen Bao +15 more
wiley +1 more source
An Iontronic Bimodal Afferent Nerve for Cross‐Modal Neuromorphic Fusion and Robotic Sorting
A flexible iontronic pressure–temperature sensor is integrated with pulse encoding and a multi‐gate SnO2 nanowire synaptic transistor to create a near‐sensor neuromorphic platform. Pressure and temperature cues are encoded, temporally integrated, and fused for accurate multimodal object recognition and robotic sorting, establishing a compact pathway ...
Mengkang Deng +10 more
wiley +1 more source
Interface‐mediated CsCuCl3 memristors achieve self‐rectification and tunable thresholds, enabling selector‐free 8 × 8 arrays with > 105 ON/OFF and > 104 rectification. Supporting dual‐mode neuromorphic computing, negative thresholds preserve low‐light recognition accuracy (91%), while positive thresholds enable sparsity‐aware edge computing.
Qingwei Shi +9 more
wiley +1 more source
FPGA-specific accurate and approximate compressor-based multipliers using column restructuring and post-synthesis approximation. [PDF]
Mir MS, Khurshid B.
europepmc +1 more source
Efficient Testable Bit Parallel Multipliers over GF(2^m) with Constant Test Set
We present a C-testable method for detecting stuck-at (s-a) faults in the polynomial basis (PB) bit parallel multiplier circuits over GF(2m). It requires only 7 tests for detecting faults to provide 100% fault coverage, which is independent of the ...
Dhiraj, Pradhan +2 more
core
Targeting a Calcium‐Associated Mitochondrial Vulnerability in TET2‐Deficient Myeloid Cells
Reduced TET2 function creates a calcium‐associated mitochondrial vulnerability in macrophages that is preferentially exploited by Lanatoside C. The resulting stress promotes apoptosis of TET2‐deficient macrophages, reduces inflammatory and fibrotic injury in human cardiac organoids, and highlights a genotype‐associated myeloid liability that may be ...
Yue Wang +18 more
wiley +1 more source
Hybrid approximate multiplier architectures for low power DWT image compression. [PDF]
Anitha R, Sridevi S.
europepmc +1 more source

