Results 131 to 140 of about 1,893,473 (266)

High speed 16-bit multiplier design

, 2013
Nowadays, in the very-large-scale integration (VLSI) systems, high speed arithmetic circuits are required, such as adders and multipliers, which are extensively and frequently used.
Zhou, Jiong.
core  

Efficient In‐Hardware Matrix–Vector Multiplication and Addition Exploiting Bilinearity of Schottky Barrier Transistors Processed on Industrial FDSOI

Advanced Electronic Materials, EarlyView.
ABSTRACT Machine learning and Artificial Intelligence (AI) tasks have stretched traditional hardware to its limits. In‐hardware computation is a novel approach that aims to run complex operations, such as matrix–vector multiplication, directly at the device level for increased efficiency.
Juan P. Martinez, Niladri Bhattacharjee, Yuxuan He, Giulio Galderisi, Brojogopal Sapui, Sara Mannaa, Ian O'Connor, Violetta Sessi, Peter Javorka, Thomas Mikolajick, Jens Trommer   +10 more
wiley   +1 more source

A scalable automated framework for multiply-accumulate unit design in high-performance computing applications. [PDF]

Sci Rep
Venkatachalam A, Seerengasamy U, Ponraj AS.   +2 more
europepmc   +1 more source

On the Role of Preprocessing and Memristor Dynamics in Reservoir Computing for Image Classification

Advanced Electronic Materials, EarlyView.
ABSTRACT Reservoir computing (RC) is an emerging recurrent neural network architecture that has attracted growing attention for its low training cost and modest hardware requirements. Memristor‐based circuits are particularly promising for RC, as their intrinsic dynamics can reduce network size and parameter overhead in tasks such as time‐series ...
Rishona Daniels, Duna Wattad, Ronny Ronen, David Saad, Shahar Kvatinsky   +4 more
wiley   +1 more source

Modified vedic multiplier architecture using Nikhilam and Karatsuba algorithms with hybrid adders for enhanced performance. [PDF]

Sci Rep
A S, A S.
europepmc   +1 more source

A low complexity and a low latency bit parallel systolic multiplier over GF(2 m ) using an optimal normal basis of type II

, 2003
Using the self duality of an optimal normal basis (ONB) of type II, we present a bit parallel systolic multiplier over GF (2 m) which has a low hardware complexity and a low latency.
Soonhak Kwon
core  

The Influence of Residual Ion Drift During Programming of Chip‐Integrated Nanoscale HfO2‐Based Memristive Devices

Advanced Electronic Materials, EarlyView.
1T1R‐arrays combining filamentary‐type memristors and CMOS transistors offer great potential for energy‐efficient analog hardware accelerators. Here, transient SET analysis of nanoscale HfO2 memristors integrated on 180 nm CMOS wafers is discussed.
Oliver Artner, Felix Cüppers, Seokki Son, Yang Chen, Xiaohua Liu, Christopher Bengel, Dennis Nielinger, André Zambanini, Stefan Wiefels, Stephan Menzel, Regina Dittmann, Susanne Hoffmann‐Eifert   +11 more
wiley   +1 more source

Stochastic‐MTJ Sampler Arrays for In‐Array Monte–Carlo Estimation

Advanced Electronic Materials, EarlyView.
A low‐energy‐barrier magnetic tunnel junction array is operated as a probability‐domain sampler: each cell's random switching, programmed through a shared digital‐to‐analog converter, makes the per‐column multiply–accumulate an unbiased Monte–Carlo expectation estimator that returns both a mean and a calibrated uncertainty.
Ran Zhang, Nellie Laleni, Sina Ranjbar, Andreas Tsiougkos, Nandakishor Yadav, Vasilis Pavlidis, Thomas Kämpfe   +6 more
wiley   +1 more source

EFFICIENT IMPLEMENTATION OF BIT PARALLEL FINITE FIELD MULTIPLIERS

International Journal of Research in Engineering and Technology, 2014
openaire   +1 more source

FPGA-based imprecise signed multiplier designs for high-performance image processing applications. [PDF]

Sci Rep
Hassan J, Khurshid B, Banday SA, Algarni A.   +3 more
europepmc   +1 more source