Results 121 to 130 of about 1,893,473 (266)

Model based optimal bit allocation [PDF]

Modeling of the operational rate-distortion characteristics of a signal can significantly reduce the computational complexity of an optimal bit allocation algorithm.
Rajpoot, Nasir M. (Nasir Mahmood)
core  

Model‐Based Time‐Modulated Write Algorithm for 1R Analog Memristive Crossbar Arrays

Advanced Electronic Materials, EarlyView.
A novel model‐based time‐modulated write algorithm efficiently programs analog 1R memristive crossbar arrays by varying pulse duration at a fixed voltage. By leveraging a physics‐based compact model and a dynamic gain mechanism, this approach overcomes device nonlinearities and parasitic effects.
Richard Schroedter, Ahmet Samil Demirkol, Ioannis Messaris, Christian Bruchatz, Eter Mgeladze, Stefan Slesazeck, Thomas Mikolajick, Ronald Tetzlaff   +7 more
wiley   +1 more source

Dynamic energy-aware fixed-point linear mapping multiplier for internet of things edge devices. [PDF]

Sci Rep
Wu D, Zhao L, Kim B, Yin J, Xue J.
europepmc   +1 more source

A Hybrid Radix-4/Radix-8 LOWPower, High Speed Multiplier Architecture for Wide Bit Widths

, 2008
– A hybrid radix-4/radix-8 architecture targeted for high bit multipliers is presented as a compromise between the high speed of a radix-4 multiplier architecture and the low power dissipation of a radix-8 multiplier architecture.
Brian S. Cherkauerl, Eby G. Friedrnan
core  

Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference

Advanced Electronic Materials, EarlyView.
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho, Dae‐won Kim, Yujin Kim, Jung‐Heum Na, Yuwon Jeong, Dong‐Yeop Lee, Shinhyun Choi   +6 more
wiley   +1 more source

An efficient multiplier-based FPGA CNN accelerator for Parkinson's disease detection using hand-drawn circle images. [PDF]

Front Artif Intell
A V, Sathasivam S, Ramachandran P.
europepmc   +1 more source

Ultra‐Low Power Consumption and Highly Durability in Sm:HfO2 Thin Film Ferroelectric Memristor for Edge Detection

Advanced Electronic Materials, EarlyView.
ABSTRACT With the continuous development of computer image processing, developing efficient and low‐power computing devices has become a key challenge. Memristors have integrated in‐situ storage and computing capabilities, making them an ideal choice for low‐power image processing computing architectures. However, current memristors are confronted with
Tengyu Li, YongRui Wang, Weifeng Zhang, Jikang Xu, Xiaobing Yan   +4 more
wiley   +1 more source

Heuristic optimization of multiplierless decimation filter for multi-standard wireless applications. [PDF]

Sci Rep
Abinaya A, Maheswari M, Khan AA, Dheenathayalan S, Kamal S, Ullah F, Karthikeyan N.   +6 more
europepmc   +1 more source

People Counting and Positioning Using Low‐Resolution Infrared Images for FeFET‐Based In‐Memory Computing

Advanced Electronic Materials, EarlyView.
In this work, low‐resolution infrared imaging is combined with a 28 nm FeFET IMC architecture to enable compact, energy‐efficient edge inference. MLC FeFET devices are experimentally characterized, and controlled multi‐level current accumulation is validated at crossbar array level.
Alptekin Vardar, Li Zhang, Alexander Rehmer, Marc Lupp, Subhashree Baskaran, Osama Abdelaal, Franz Müller, Nandakishor Yadav, Bing Li, Thomas Kämpfe   +9 more
wiley   +1 more source

An In-Ear Sleep Modulation SoC Featuring a CNN-LSTM Accelerator with Long-Kernel Memory Reuse and Runtime Dynamic Quantization. [PDF]

Dig Tech Pap (N Y)
Xu Y, Chen X, Hou Y, Xu J, You H, Huang Y, Liu B, Hung A, Richardson AG, Genov R, Liu X.   +10 more
europepmc   +1 more source