Results 211 to 220 of about 1,893,473 (266)
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New Efficient Bit-Parallel Polynomial Basis Multiplier for Special Pentanomials
The Integration VLSI Journal, 2014We present a bit-parallel polynomial basis multiplier based on a new divide-and-conquer approach using squaring. In particular, we apply the proposed approach to special types of irreducible pentanomials called as types I and II pentanomials, and induce explicit formulae and complexities of the proposed multiplier for these types of pentanomials.
Ku-Young Chang, Dowon Hong, Changho Seo
exaly +3 more sources
Low Complexity Bit-Parallel Multipliers Based on a Class of Irreducible Pentanomials
IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2006In this paper, we consider the design of bit-parallel canonical basis multipliers over the finite field GF(2m) generated by a special type of irreducible pentanomial that is used as an irreducible polynomial in the Advanced Encryption Standard (AES). Explicit formulas for the coordinates of the multiplier are given.
Roman Hermida, Francisco Tirado
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Low Complexity Bit-Parallel Multiplier for a Class of Finite Fields
2006 International Conference on Communications, Circuits and Systems, 2006This short paper summarizes our recent results on construction of low-complexity bit-parallel finite field multiplier using polynomial basis. The complexity and time delay of the proposed multipliers are lower than those of the similar proposals.
Huapeng Wu
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Efficient Bit-Parallel Multiplier for Irreducible Pentanomials Using a Shifted Polynomial Basis
IEEE Transactions on Computers, 2006In this paper, we present a bit-parallel multiplier for GF(2m ) defined by an irreducible pentanomial xm+xk 3 +xk 2+xk 1+1, where 1lesk 1 lesk2 lesk3 lesm/2. In order to design an efficient, bit-parallel multiplier, we introduce a shifted polynomial basis and modify a reduction matrix presented by Reyhani-Masoleh and Hasan.
Ku-Young Chang, Dowon Hong, Sun-Mi Park
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An Efficient CRT-based Bit-parallel Multiplier for Special Pentanomials. [PDF]
IACR Cryptol. ePrint Arch., 2020 The Chinese remainder theorem (CRT)-based multiplier is a new type of hybrid bit-parallel multiplier, which can achieve nearly the same time complexity compared with the fastest multiplier known to date with reduced space complexity. However, the current
Yin Li 0001, Yu Zhang 0031
core +3 more sources
SOS CMOS 16 Bit Parallel Multiplier
Japanese Journal of Applied Physics, 1981A high performance 16 by 16 bit parallel multiplier is presented, which features SOS CMOS configuration. Maximum multiplying time and average power are 65 ns and 250 mW (VDD=5 V), respectively. The SOS CMOS multiplier shows the best powerdelay product, compared with other device-configuration multipliers reported.
Masao Fukuma, Yasuo Ohno, Yuji Okuto
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Efficient Bit-Parallel Multipliers in Composite Fields
2008 IEEE Asia-Pacific Services Computing Conference, 2008Hardware implementation of multiplication in finite field GF(2m) based on sparse polynomials is found to be advantageous in terms of space-complexity as well as the time-complexity. In order to design multipliers for the composite fields, we have found another permutation polynomial to convert irreducible polynomials into like-trinomials of the forms ...
Chiou-Yng Lee, Pramod Kumar Meher
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A GaAs 16x16 bit parallel multiplier
IEEE Journal of Solid-State Circuits, 1983A GaAs 16/spl times/16-bit parallel multiplier has been constructed using a direct-coupled FET logic (DCFL) circuit with tungsten silicide gate self-aligned technology. This circuit chip, containing 3168 NOR gates with 2-/spl mu/m gate length enhancement/depletion FETs, is the most complex GaAs integrated circuit reported to date. MESFETs with the gate
Y. Nakayama +6 more
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Bit-parallel finite field multipliers for irreducible trinomials
IEEE Transactions on Computers, 2006A new formulation for the canonical basis multiplication in the finite fields GF(2/sup m/) based on the use of a triangular basis and on the decomposition of a product matrix is presented. From this algorithm, a new method for multiplication (named transpositional) applicable to general irreducible polynomials is deduced.
José Luis Imaña +2 more
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32 Bit Parallel Multiplier Using VHDL
International Journal of Engineering Trends and Technology, 2014In this paper, design of 32-bit parallel multiplier is presented, by introducing Carry Save Adder (CSA) in partial product lines. The multiplier given in this paper is modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. Here comparison is done between Carry Save Adder (CSA) and Carry Look Ahead Adder
Vrushali Gaikwad +4 more
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