Results 231 to 240 of about 1,893,473 (266)

Bit-parallel multipliers for different irreducible polynomials in finite fields

2016 7th IEEE International Conference on Software Engineering and Service Science (ICSESS), 2016
Multiplications in finite fields are crucial due to the fact that they are widely used in areas of cryptography. We propose bit-parallel multipliers in finite fields for trinomials, Equally-Spaced-Polynomials (ESPs), pentanomials, All-One-Polynomials (AOPs), and Successive-One-Polynomials (SOPs).
null Haibo Yi, null Weijian Li, null Zhe Nie   +2 more
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Bit-Parallel Polynomial Basis Multiplier for New Classes of Finite Fields

IEEE Transactions on Computers, 2008
In this paper, three small classes of finite fields GF(2m) are found for which low complexity bit-parallel multipliers are proposed. The proposed multipliers have lower complexities compared to those based on the irreducible pentanomials. It is also shown that there does not always exist an irreducible all-one polynomial, equally-spaced polynomial, or ...
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Multiplexer-based bit-parallel systolic multipliers over GF(2m)

Computers & Electrical Engineering, 2008
Two novel systolic architectures are presented in this paper for polynomial basis finite field multipliers. Using cut-set systolization technique and modified Booth's recording, we have derived here an efficient realization of multiplexer-based bit-parallel systolic multipliers over GF(2^m).
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A high-speed LSI GaAs 8x8 bit parallel multiplier

IEEE Journal of Solid-State Circuits, 1982
Multiplication is frequently the speed-limiting function in digital signal processing systems. High-speed hardware multiplier ICs can therefore greatly enhance the throughput and bandwidth of many digital systems. In this paper, the design, fabrication, and performance of GaAs parallel multipliers are discussed.
F.S. Lee, G.R. Kaelin, B.M. Welch, R. Zucca, E. Shen, P. Asbeck, C.G. Kirkpatrick, S.I. Long, R.C. Eden   +8 more
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Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m})

25th IEEE VLSI Test Symmposium (VTS'07), 2007
This paper presents a C-testable technique for detecting transition faults with 100% fault coverage in the polynomial basis (PB) bit parallel (BP) multiplier circuits over GF(2m). The proposed technique requires only 10 vectors, which is independent of multiplier size, at the cost of 6% (avg.) extra hardware and three control pins.
Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan   +3 more
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Performance evaluation of 3-D stacked 32-bit parallel multipliers

ACM SIGARCH Computer Architecture News, 2013
Conventional two-dimensional (2-D) implementation technologies face certain limitations; to overcome these limitations, three-dimensional (3-D) integration technologies have been developed. There has been a focus on circuit partitioning strategies because they play an important role in exploiting the potential of 3-D stacked circuits.
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Technology optimised fixed-point bit-parallel multiplier for LUT-based FPGAs

International Journal of High Performance Systems Architecture, 2016
Modern day field programmable gate arrays FPGA have look-up tables LUT as inherent basic logic elements. With FPGAs fast moving from prototype designing to low and medium volume productions, there is an increased need for efficient utilisation of these FPGA primitives.
Burhan Khurshid, Roohie Naaz Mir
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Fault tolerant bit parallel finite field multipliers using LDPC codes

2008 IEEE International Symposium on Circuits and Systems (ISCAS), 2008
Motivated by the problems associated with soft errors in digital circuits and fault related attacks in cryptographic hardware, we presented a systematic method for designing single error correcting multiplier circuits for finite fields or Galois fields over GF(2m) in [7]. We used multiple parity predictions to correct single errors based on the Hamming
Jimson Mathew, Jawar Singh, Abusaleh M. Jabir, Mohammad Hosseinabady, Dhiraj K. Pradhan   +4 more
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Bit-parallel finite field multiplier and squarer using polynomial basis

IEEE Transactions on Computers, 2002
Bit-parallel finite field multiplication using polynomial basis can be realized in two steps: polynomial multiplication and reduction modulo the irreducible polynomial. In this article, we present an upper complexity bound for the modular polynomial reduction.
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Low-complexity bit-parallel systolic multipliers over GF(2 )

Integration, 2008
This paper presents new time-dependent and time-independent multiplication algorithms over finite fields GF(2m) by employing an interleaved conventional multiplication and a folded technique. The proposed algorithm allows efficient realization of the bit-parallel systolic multipliers. The results show that the proposed time-independent multiplier saves
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