Results 241 to 250 of about 1,893,473 (266)
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Ringed bit-parallel systolic multipliers over a class of fields GF(2 )
Integration, 2005This paper presents ringed bit-parallel systolic multipliers for computing AB+C over a class of finite fields GF(2^m), in which all elements are represented using a root of an all-one polynomial or an equally spaced polynomial. Compared to other related multipliers, the proposed multipliers reveal properties of lower hardware complexity, lower latency ...
Yeun-Renn Ting, Erl-Huei Lu, Ya-Cheng Lu
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Improving reliability for bit parallel finite field multipliers using Decimal Hamming
2010 East-West Design & Test Symposium (EWDTS), 2010Technology evolution dictates ever increasing density of transistors in chips, lower power consumption and higher performance. In such environment occurrence of multiple-bit upsets (MBUs) is a concern. That, together with the presence of fault-related attacks in cryptographic Hardware act as our motivation. The outcome of which, being presented in this
Nikolaos Mavrogiannakis +2 more
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An Efficient CRT-Based Bit-Parallel Multiplier for Special Pentanomials
IEEE Transactions on Computers, 2022Yin Li 0001, Xinyuan Cui, Yu Zhang 0031
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CMOS/SOS 16-Bit Parallel Multiplier and Adder-Subtractor
ESSCIRC 80: 6th European Solid State Circuits Conference, 1980Two high performance CMOS/SOS devices for use in digital signal processing applications are described: a 16-bit parallel multiplier featuring a novel logic implementation and a 3 × 8-bit adder-subtractor circuit.
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Reed-Solomon Decoder Architecture Using Bit-Parallel Systolic Multiplier
2011Reed-Solomon (RS) codes play an important role in providing error protection and data integrity. Design of a scalable RS decoder is implemented with Bit-Parallel Systolic Multiplier. This bit-parallel multiplier is defined from All-One Polynomial. This can perform higher data throughput rate with shorter latency.
Suvarna K. Gosavi +2 more
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Efficient Bit-Parallel GF(2^m) Multiplier for a Large Class of Irreducible Pentanomials
IEEE Transactions on Computers, 2009This work studies efficient bit-parallel multiplication in GF(2m) for irreducible pentanomials, based on the so-called shifted polynomial bases (SPBs). We derive a closed expression of the reduced SPB product for a class of polynomials xm + xk s + xk s-1+ hellip + xk-1 + 1, with ks - k1 les m+1/ 2.
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Speedup of bit-parallel Karatsuba multiplier in generated by trinomials
Information Processing Letters, 2011Yin Li, Gong-liang Chen, Jian-hua Li
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A 4x4 Bit Parallel Multiplier with GaAs JFET DCFL
Extended Abstracts of the 1983 International Conference on Solid State Devices and Materials, 1983Y. Kato +9 more
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Ringed Bit-Parallel Systolic Multipliers Over a Class of Fields GF(2m)
The Integration VLSI Journal, 2005Erl-Huei Lu, Yeun-Renn Ting
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