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Easily Testable Implementation for Bit Parallel Multipliers in GF (2m)
2006 IEEE International High Level Design Validation and Test Workshop, 2006A testable implementation of bit parallel multiplier over the finite field GF(2m) is proposed A function independent test set of length (2m+4), which detects all the single stuck-at faults in an m bit GF(2m) multiplier circuit, is also presented. Test set can be determined readily from the corresponding algebraic forms without running an ATPG tool The ...
Hafizur Rahaman 0001 +3 more
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Low complexity bit-parallel multipliers for a class of finite fields
IEEE Transactions on Computers, 1998New implementations of bit-parallel multipliers for a class of finite fields are proposed. The class of finite fields is constructed with irreducible AOPs (all one polynomials) and ESPs (equally spaced polynomials). The size and time complexities of our proposed multipliers are lower than or equal to those of the previously proposed multipliers of the ...
Huapeng Wu, M. Anwarul Hasan
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Design of Bit Parallel Multiplier with Lower Time Complexity
2004Recently efficient implementation of finite field operations has received a lot of attention. Among GF(2 m ) arithmetic operations, a multiplication process is the most basic and a critical operation that determines a speed-up in hardware. Mastrovito multipliers using a trinomial p(x)=x m +x n +1(n≠ m/2) require m 2-1 XOR gates and m 2 AND gates.
Seon Ok Lee +5 more
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New bit-parallel systolic multipliers for a class of GF(2/sup m/)
ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), 2002The operations of the cyclic shifting and the inner product are defined based on the properties of irreducible all one polynomials. With the two operations, an effective algorithm for computing multiplications over a class of GF(2/sup m/) was developed in this paper. The low complexity bit-parallel systolic multiplier is presented.
Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee
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Technology-Optimized Fixed-Point Bit-Parallel Multipliers for FPGAs
Journal of Signal Processing Systems, 2016Modern day field programmable gate arrays have carry-chains and look-up tables as the basic logic elements. Efficient realization of different arithmetic circuits on FPGAs demands an improved mapping of different functionalities onto these logic elements.
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Low-Complexity Bit-Parallel Systolic Multipliers over GF(2m)
2006 IEEE International Conference on Systems, Man and Cybernetics, 2006Recently, cryptographic applications based on finite fields have attracted much interest. This paper presents two new algorithms, called time-dependent and time-independent multiplication algorithms over a finite field GF(2m) by employing an interleaved conventional multiplication and a folded technique.
Chiou-Yng Lee +3 more
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High-speed architectures for GHASH based on efficient bit-parallel multipliers
2010 IEEE International Conference on Wireless Communications, Networking and Information Security, 2010GHASH is the authentication part of Galois Counter Mode (GCM) which can provide encryption and authentication simultaneously, its core is based on the GF(2128) multiplier. A four-parallel architecture for GHASH which is applied to authentication for high-speed access networks is proposed, and its core GF(2128) multiplier is implemented by two kinds of ...
Jimei Wang +3 more
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Efficient bit-parallel multipliers over finite fields GF(2m)
Computers & Electrical Engineering, 2010Hardware implementation of multiplication in finite field GF(2^m) based on sparse polynomials is found to be advantageous in terms of space-complexity as well as the time-complexity. In this paper, we present a new permutation method to construct the irreducible like-trinomials of the form (x+1)^m+(x+1)^n+1 for the implementation of efficient bit ...
Chiou-Yng Lee, Pramod Kumar Meher
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Fast Bit-Parallel GF(2^n) Multiplier for All Trinomials
IEEE Transactions on Computers, 2005Based on a new representation of GF(2/sup n/), we present two multipliers for all irreducible trinomials. Space complexities of the multipliers match the best results. The time complexity of one multiplier is T/sub A/ + (1 + [log/sub 2/ n])T/sub X/ for all irreducible trinomials, where T/sub A/ and T/sub X/ are the delay of one 2-input AND and XOR ...
Haining Fan, Yiqi Dai
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A 280-ps Josephson 4-bitx4-bit parallel multiplier
IEEE Journal of Solid-State Circuits, 1985The multiplier circuit is implement in 5-/spl mu/m Resistor Coupled Josephson Logic (RCJL) and uses dual-rail logic aiming for high-speed operation. The array configuration was adopted for its design simplicity. The circuit contains 249 gates consisting of 862 Josephson junctions.
J. Sone, J. Tsai, H. Abe
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