Results 41 to 50 of about 1,893,473 (266)

Multimode Oxide‐Based Optoelectronic Memtransistor for In‐Sensor Vision Processing

Advanced Functional Materials, EarlyView.
A multimode optoelectronic memtransistor (OEMT) is demonstrated for vision explainable artificial intelligence (VXAI) hardware. By integrating optical sensing, electrical masking, and non‐volatile memory, the device enables key operations required for generating saliency information.
Min Gu Lee, Geunyoung Kim, Hwa Young Kim, Do Hoon Kim, Hanchan Song, Huisu Noh, Jungwan Noh, Seungwoo Lee, Sang‐Hee Ko Park, Himchan Cho, Kyung Min Kim   +10 more
wiley   +1 more source

Multimodal Optoelectronic Synapses for Neuromorphic Intelligence: Coupling Light, Electrical, Thermal, and Beyond

Advanced Functional Materials, EarlyView.
This review revisits optoelectronic neuromorphic devices that extend from unimodal sensing toward multimodal perception. Five types of stimuli‐to‐output information flow that are classified based on the device roles within the system and applications are summarized and discussed.
Jihyun Shin, Junhyung Cho, Wangmyung Choi, Jaehyun Hur, Jae Kyeong Jeong, Ulrike Kraft, Hocheon Yoo   +6 more
wiley   +1 more source

Efficient bit-parallel multiplier for finite field of trinomial using SPB and its weakly dual basis(不可约三项式有限域的高速并行比特乘法器)

Zhejiang Daxue xuebao. Lixue ban, 2010
在移位多项式的弱共轭基底的理论推导的基础上,提出了一种有限域上的并行比特乘法器的新结构.在由不可约三项式f(x)=xm+xk+ 1生成的域内,此种结构的并行比特乘法器需要m2个与门和m2 — 1个异或门.在同样的空间复杂度下,时间复杂度降低为,具有最短的关键路径.
LIDa-wei(李大为), LONGYan-chen(龙彦辰), SHENHai-bin(沈海斌)   +2 more
doaj   +1 more source

Strong Lead‐Free Bioinspired Piezoceramics for Durable Energy Transducers

Advanced Functional Materials, EarlyView.
We fabricated brick‐and‐mortar lead‐free piezoceramics with Bi0.5Na0.5TiO3 monocrystal platelets as bricks and amorphous silica as mortar. The alignment of the bricks and the presence of the amorphous silica led to anisotropic residual stresses. These residual stresses increase the samples toughness, strength and durability while the brick alignment ...
Ruxue Yang, Temesgen Tadeyos Zate, Peiren Wang, Soumyajit Mojumder, Elo Overgaard Mogensen, Oriol Gavalda‐Diaz, Zihe Li, Shitong Zhou, Ajeet Kumar, James Roscow, Hamideh Khanbareh, Astri Bjørnetun Haugen, Florian Bouville   +12 more
wiley   +1 more source

Design of Radix-8 Unsigned Bit Pair Recoding Algorithm-Based Floating-Point Multiplier for Neural Network Computations

IEEE Access
The neural network computations for Artificial Intelligence (AI) applications demand high speed, low power and area-efficient Floating-Point (FP) multiplication.
J. Jean Jenifer Nesam, S. Sankar Ganesh
doaj   +1 more source

Efficient Realization of BCD Multipliers Using FPGAs

International Journal of Reconfigurable Computing, 2017
In this paper, a novel BCD multiplier approach is proposed. The main highlight of the proposed architecture is the generation of the partial products and parallel binary operations based on 2-digit columns.
Shuli Gao, Dhamin Al-Khalili, J. M. Pierre Langlois, Noureddine Chabini   +3 more
doaj   +1 more source

Memristive‐Gated RC‐Delay Synaptic Transistors for Time‐Encoded Analog in‐Memory Computing

Advanced Functional Materials, EarlyView.
A Memristive‐Gated Transistor for Time‐Encoded Analog In‐Memory Computing — By exploiting the RC delay of a self‐rectifying interface‐type memristor, nonlinear I–V distortion is structurally bypassed, enabling 3‐bit nonvolatile memory, spike‐timing‐based analog encoding, and hardware‐calibrated reservoir‐computing validation within a unified device ...
Yun‐Seo Shin, Eunjoo Yoo, Ki‐Hoon Son, Hyun‐Sik Kim, Dae‐Hee Han, Jeong Hyeon Son, Seung Hwan Lee, Hong‐Sub Lee   +7 more
wiley   +1 more source

RSFQ Parallel Multiplier

, 2003
This work presents the design of RSFQ parallel multiplier suitable for implementation of the superconducting digital signal processor for interference cancellation in 3G cellular systems.
Tolkacheva, Elena,, Kidiyarova-Shevchenko, Anna,, Engseth, Henrik,, Kataeva, Irina,   +3 more
core   +1 more source

A bit multiplier.

, 2013
(A) Truth table for bit binary multiplier. (B) Schematic of the binary oscillator bit multiplier using oscillators based on standard circuitry.
Jon Borresen (298275), Stephen Lynch (298276)   +1 more
core   +1 more source

Emerging Post‐CMOS Hardware Neurons for Brain‐Inspired Computing: Devices, Circuits, and System Integration

Advanced Functional Materials, EarlyView.
The physical realization of artificial neurons is a critical challenge for energy‐efficient neuromorphic computing. This review presents a comprehensive analysis of the evolution of artificial neuron implementations from conventional CMOS to emerging post‐CMOS technologies.
Kannan Udaya Mohanan, Hocheon Yoo, Benoît H. Lessard, Ioannis Kymissis, Chang‐Hyun Kim   +4 more
wiley   +1 more source