Results 21 to 30 of about 1,893,473 (266)
Heliyon, 2023 An novel method to generate 40-tupling frequency millimeter (MMW) based on the remodulation of MZMs and a novel radio over fiber (ROF) system to transmit the generated MMW are proposed.
Xinqiao Chen +6 more
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Low-latency bit-parallel systolic multiplier
Electronics Letters, 1993 A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented. The proposed scheme yields significantly lower latency compared to existing systolic multipliers, without increasing the circuit complexity. High throughput is achieved, limited by the delay of a gated full adder and a latch.
K.Z. Pekmestzi, C. Caraiscos
openaire +1 more source
An interleaved ZVS ultra‐large gain converter for sustainable energy systems applications
IET Power Electronics, 2021 This paper proposes an interleaved zero‐voltage switching (ZVS) ultra‐large gain converter. By implementing coupled‐inductor (CI) and built‐in transformer (BIT) together with a switched capacitor (SC) voltage multiplier cell (VMC), a higher degree of ...
Alireza Bagherian +3 more
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Efficient Square-Based Montgomery Multiplier for All Type C.1 Pentanomials
IEEE Access, 2018 In this paper, we present a low complexity bit-parallel Montgomery multiplier for $GF(2^{m})$ generated with irreducible Type C.1 pentanomials $x^{m}+x^{m-1}+x^{k}+x+1$ . Based on a combination of generalized polynomial basis (GPB) squarer and a newly
Yin Li, Xingpo Ma, Qing Chen, Chuanda Qi
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Space Efficient
IEEE Access, 2020 Recently, new multiplication schemes over the binary extension field GF(2m) based on an n-term Karatsuba algorithm have been proposed for irreducible trinomials. In this paper, we extend these schemes for trinomials to any irreducible polynomials.
Sun-Mi Park +3 more
doaj +1 more source
Bit-Level Systolic Architecture for a Matrix-Matrix Multiplier [PDF]
, 2012 Highly efficient arithmetic operations are necessary to achieve the desired performance in many real-time systems and digital image processing applications.
Padhy, Binayak +7 more
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Low Space Complexity
IEEE Access, 2019 We propose bit-parallel GF(2m) multipliers for irreducible trinomials using an n-term Karatsuba algorithm and Mastrovito approach, which are generalizations of the newly proposed multiplication scheme for a specific trinomial.
Sun-Mi Park +3 more
doaj +1 more source
Bi-parameter Potential theory and Carleson measures for the Dirichlet space on the bidisc
Discrete Analysis, 2023 Bi-parameter potential theory and Carleson measures for the Dirichlet space on the bidisc, Discrete Analysis 2023:22, 58 pp. Carleson measures arise naturally when considering harmonic or holomorphic extensions from the boundary of a domain to the ...
Nicola Arcozzi +3 more
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A low-power high-radix serial-parallel multiplier
, 2007 In this paper, we introduce a novel high-radix binary signed digit (BSD) serial-parallel multiplier suitable for low-power high-speed multiplication. The proposed N- bittimesN-bit radix-16 serial-parallel multiplier can reduce the number of accumulation ...
Richard M. Jiang +3 more
core +4 more sources
An 8-bit Radix-4 Non-Volatile Parallel Multiplier
, 2021 The data movement between the processing and storage units has been one of the most critical issues in modern computer systems. The emerging Resistive Random Access Memory (RRAM) technology has drawn tremendous attention due to its non-volatile ability ...
Kejie Huang +3 more
core +1 more source