Results 1 to 10 of about 99 (92)
N-Term Karatsuba Algorithm and its Application to Multiplier Designs for Special Trinomials [PDF]
IEEE Access, 2018 In this paper, we propose a new type of non-recursive Mastrovito multiplier for GF(2m) using an n-term Karatsuba algorithm (KA), where GF(2m) is defined by an irreducible trinomial, xm+xk +1, m = nk.
Yin Li, Yu Zhang, Xiaoli Guo, Chuanda Qi
doaj +5 more sources
Fast Bit-Parallel Binary Multipliers Based on Type-I Pentanomials
IEEE Transactions on Computers, 2018 In this paper, a fast implementation of bit-parallel polynomial basis (PB) multipliers over the binary extension field GF(2^m) generated by type-I irreducible pentanomials is presented. Explicit expressions for the coordinates of the multipliers and a detailed example are given.
José Luis Imaña Pascual
exaly +3 more sources
Egyptian Informatics Journal, 2022 Encryption schemes like AES require finite field modular multiplication. The encryption speed is highly dependent on the performance of the finite field multiplier.
Sakshi Devi, Rita Mahajan, Deepak Bagai
doaj +1 more source
A Bit-Parallel Deterministic Stochastic Multiplier
2023 24th International Symposium on Quality Electronic Design (ISQED), 2023 This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6$\times$10$^4$, while improving the computational error by 32.2\%, compared to three prior stochastic multipliers.
Sairam Sri Vatsavai, Ishan G. Thakkar
openaire +3 more sources
Mathematics, 2022 Security and privacy issues with IoT edge devices hinder the application of IoT technology in many applications. Applying cryptographic protocols to edge devices is the perfect solution to security issues.
Atef Ibrahim +5 more
doaj +1 more source
A Single-Stage 12-Times Frequency Multiplier for a 5G Frequency Synthesizer [PDF]
Journal of Electromagnetic Engineering and Science, 2022 This paper presents a single-stage 12-times frequency multiplier composed of an invented harmonic generator (HG) and a modified cascode buffer. The reliable output frequency band is guaranteed from 16 GHz to 28 GHz (54.5% frequency range). The whole band
SungWoo Im, Kyu-Hyun Nam, Junseok Park
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Mathematics, 2022 The use of IoT technology in several applications is hampered by security and privacy concerns with IoT edge nodes. Security flaws can only be resolved by implementing cryptographic protocols on these nodes.
Atef Ibrahim +3 more
doaj +1 more source
The Journal of Engineering, 2023 The continued quest for finding a low‐power and high‐performance hardware algorithm for signed number multiplication led to designing a simple and novel radix‐8 signed number multiplier with 3‐bit grouping and partial product reduction performed using ...
Naga Venkata Vijaya Krishna Boppana +1 more
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Power-Intent Systolic Array Using Modified Parallel Multiplier for Machine Learning Acceleration
Sensors, 2023 Systolic arrays are an integral part of many modern machine learning (ML) accelerators due to their efficiency in performing matrix multiplication that is a key primitive in modern ML models.
Kashif Inayat +5 more
doaj +1 more source
On Low Complexity Bit Parallel Polynomial Basis Multipliers [PDF]
, 2003 Representing finite field elements with respect to the polynomial (or standard) basis, we consider a bit parallel multiplier architecture for the finite field GF(2 m ) . Time and space complexities of such a multiplier heavily depend on the field defining irreducible polynomials.
Arash Reyhani-Masoleh, M. Anwarul Hasan
openaire +2 more sources