Results 11 to 20 of about 1,893,473 (266)
Integration of Reconfigurable p-Bit and 1R Crossbar Array for Memristive Probabilistic Computing. [PDF]
Adv Sci (Weinh)A memristive probabilistic computing system is demonstrated by integrating stochastic p‐bits based on volatile memristors with a 1R crossbar array encoding interaction weights. The system performs weighted‐sum operations across the array and updates p‐bits iteratively.
Soh K +7 more
europepmc +2 more sources
Design and optimization of a quaternary booth multiplier in quaternary logic using carbon nanotube transistors [PDF]
Scientific ReportsEmploying the Booth algorithm to generate partial products and utilizing the Wallace tree method for compressing these products significantly enhance the speed of multipliers.
Sobhan Aghamalizadeh toosanloo +1 more
doaj +2 more sources
Design and synthesis of reversible Vedic multiplier using cadence 180 nm technology for low-power high-speed applications [PDF]
Scientific ReportsWith the evolving modern-day communication applications, there is a need for an effectively improved performance in multiplication operations. In today’s scenario, multiplication operations based on Vedic mathematics have the primary advantage that the ...
Narayanan Mageshwari +2 more
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Device Stochasticity Directly Implements Bayesian Sampling in Spiking Neurons. [PDF]
Adv Sci (Weinh)Brain‐inspired stochastic spiking turns device noise into Bayesian uncertainty for robust, low‐power neuromorphic computing. ABSTRACT Device stochasticity is considered a non‐ideality in neuromorphic hardware, although stochastic neural activity supports probabilistic computation in biological systems.
Zheng H, Liu J, Yang K.
europepmc +2 more sources
Bit-level pipelined digit-serial array processors [PDF]
, 1998 A new architecture for high performance digit-serial vector inner product (VIP) which can be pipelined to the bit-level is introduced. The design of the digit-serial vector inner product is based on a new systematic design methodology using radix-2n ...
Ashur, A, Aggoun, A, Ibrahim, MK
core +1 more source
IEEE Access, 2021 Multiply-Accumulate (MAC) operation is the backbone of Least Mean Squares (LMS) digital adaptive filters. Implementing LMS on hardware platform as a Fully Dedicated Architecture (FDA) multiplier becomes bottleneck for higher order filters, prompting high
Shawez Ahmad +3 more
doaj +1 more source
ETRI Journal, 2017 Multiplication in finite fields is used in many applications, especially in cryptography. It is a basic and the most computationally intensive operation from among all such operations.
Sudha Ellison Mathe, Lakshmi Boppana
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Design of Parallel Multiplier Based on Radix-4 Booth Coding [PDF]
Zhengzhou Daxue xuebao. Gongxue banSpeed and area are two basic indexes to evaluate the performance of multiplier unit. Aiming at the problem of balancing layout area and transmission delay in current multiplier design, a new 16-bit signed fixed-point multiplier was designed by using ...
FAN Wenbing, ZHOU Jianzhang
doaj +1 more source
Decimal multiplication using compressor based-BCD to binary converter
Engineering Science and Technology, an International Journal, 2018 The objective of this work is to implement a scalable decimal to binary converter from 8 to 64 bits (i.e 2-digit to 16-digit) using parallel architecture.
Sasidhar Mukkamala +2 more
doaj +1 more source
Efficient Bit-Parallel Multiplier for All Trinomials Based on
IEEE Access, 2020 Recently, hybrid multiplication schemes over the binary extension field $GF(2^{m})$ based on $n$ -term Karatsuba algorithm (KA) have been proposed for irreducible trinomials.
Sun-Mi Park +3 more
doaj +1 more source