Results 11 to 20 of about 2,387,804 (309)

Atomic Layer Grown Zinc-Tin Oxide as an Alternative Buffer Layer for Cu2ZnSnS4-Based Thin Film Solar Cells: Influence of Absorber Surface Treatment on Buffer Layer Growth. [PDF]

open access: yesACS Appl Energy Mater, 2022
Zn1–xSnxOy (ZTO) deposited by atomic layer deposition has shown promising results as a buffer layer material for kesterite Cu2ZnSnS4 (CZTS) thin film solar cells.
Martin NM   +8 more
europepmc   +2 more sources

INVESTIGATION OF POSSIBILITY OF THE MISFIT DISLOCATION DENSITY REDUCTION IN GE/SI FILMS WITH A BUFFER LAYER

open access: yesФизико-химические аспекты изучения кластеров, наноструктур и наноматериалов, 2021
The possibility of improving the quality of Ge/Si heteroepitaxial structures with a buffer layer is investigated. It is shown that when using a preparatory layer consisting of nanostructures overgrown with a low-temperature buffer layer, it is possible ...
V.A. Lapin   +3 more
doaj   +1 more source

A multi-exit recirculating optical packet buffer [PDF]

open access: yes, 2005
We propose a new type of recirculating buffer, the multiexit buffer (MEB), for use in asynchronous optical packet switches with statistical multiplexing, operating at speeds of 40-100 Gb/s.
Vanderbauwhede, W.A.   +2 more
core   +1 more source

Effect of Cu buffer layer on magnetic anisotropy of cobalt thin films deposited on MgO(001) substrate

open access: yesAIP Advances, 2016
Cobalt thin films with 5 nm thickness were prepared on single-crystal MgO (001) substrates with different thickness Cu buffer (0 nm, 5 nm, 10 nm, 20 nm). The structure, magnetic properties and transport behaviors were investigated by employing low-energy-
Syed Sheraz Ahmad   +6 more
doaj   +1 more source

Effect Of Buffer And Spacer Layer Thicknesses On Magnetic Properties Of Co/Si/Co/GaAs Multilayer [PDF]

open access: yes, 2008
Hysteresis loop changed from two phase to single phase with decreasing Si-spacer layer thickness in Co/Si/Co/GaAs. Addition of Au buffer layer changed the phase of hysteresis loop.
Islam, J.   +4 more
core   +1 more source

Non-Toxic Buffer Layers in Flexible Cu(In,Ga)Se2 Photovoltaic Cell Applications with Optimized Absorber Thickness

open access: yesInternational Journal of Photoenergy, 2017
Absorber layer thickness gradient in Cu(In1−xGax)Se2 (CIGS) based solar cells and several substitutes for typical cadmium sulfide (CdS) buffer layers, such as ZnS, ZnO, ZnS(O,OH), Zn1−xSnxOy (ZTO), ZnSe, and In2S3, have been analyzed by a device ...
Md. Asaduzzaman   +3 more
doaj   +1 more source

Improving the photovoltage of Cu2O photocathodes with dual buffer layers

open access: yesNature Communications, 2023
Cuprous oxide (Cu2O) is a promising oxide material for photoelectrochemical water splitting (PEC), and increasing its photovoltage is the key to creating efficient overall PEC water-splitting devices. Previous reports are mostly focused on optimizing the
Jinshui Cheng, Linxiao Wu, Jingshan Luo
doaj   +1 more source

Numerical Modelling Analysis for Carrier Concentration Level Optimization of CdTe Heterojunction Thin Film–Based Solar Cell with Different Non–Toxic Metal Chalcogenide Buffer Layers Replacements: Using SCAPS–1D Software

open access: yesCrystals, 2021
Cadmium telluride (CdTe), a metallic dichalcogenide material, was utilized as an absorber layer for thin film–based solar cells with appropriate configurations and the SCAPS–1D structures program was used to evaluate the results.
Samer H. Zyoud   +3 more
doaj   +1 more source

EDX spectra of untreated, buffer layer + barrier layer, buffer layer + Ag NPs + barrier layer coatings.

open access: yes, 2023
S2 Fig reports the EDX spectra of deposited polymeric (buffer layer + barrier layer) and nanostructured coating (buffer layer + Ag NPs + barrier layer) with respect to the untreated sample.
Elena Veronesi (3203076)   +17 more
core   +1 more source

Design of BCP buffer layer for inverted perovskite solar cells using ideal factor

open access: yesAPL Materials, 2019
In the inverted structure perovskite solar cells, a buffer layer is generally used at the interface between the n-type semiconductor layer and the metal electrode, but its design guidelines have not yet been established.
Naoyuki Shibayama   +4 more
doaj   +1 more source

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