Results 131 to 140 of about 18,840,038 (173)

A 12-bit 10GS/s 16-Channel Time-Interleaved ADC with a Digital Processing Timing-Skew Background Calibration in 5nm FinFET

2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2022
A 12b 10GS/s 16-channel time-interleaved (TI) ADC with cascaded input buffers, 625MS/s voltage-current (V-I) pipelined SAR ADCs and a digital processing timing-skew background calibration is proposed. A prototype 10GS/s TI ADC in 5nm FinFET achieves 48dB
Kyoung-Jun Moon, Dong-Ryeol Oh, Younghyo Park, Kyung-Hoon Lee, Sun-Jae Park, Sungno Lee, H. Hwang, Hyunjin Shin, Young-Jae Cho, Michael Choi, Jongshin Shin   +10 more
semanticscholar   +1 more source

Emerging Memory RRAM Embedded in 12FFC FinFET Technology for industrial Applications

International Electron Devices Meeting, 2023
In this work, an embedded RRAM array extending from 40/28nm logic to 12FFC FinFET technology is firstly demonstrated. Based on comprehensive reliability analysis on 28nm RRAM.
Chun-Yu Wu, Chang-Feng Yang, Chih-Wei Lai, Yu-Tien Wu, Ta-Chun Chien, Ming-Han Yang, Ming-Ta Yang, Yu-Neng Kao, Chih-Lin Cheng, Chia-Yu Wang, H. Tseng, Y. Chih, Wen-Ting Chu, Arthur Hung, W. H. Chuang   +14 more
semanticscholar   +1 more source

Effects of Fin Height on Digital Performance of Hybrid p-Si/n-InGaAs C-FinFETs at 25 nm Gate Length

2020
We report effects of Fin height on the logic application of hybrid complementary FinFETs (HC-Fins) composed of n-FinFETs and p-FinFETs employing InGaAs and Si channel, respectively, at gate length of 25 nm. Using extensive numerical analysis, we calculate rise time tr and fall time tf of NAND gate based inverter built with HC-Fins.
Kallolini Banerjee, Abhijit Biswas
openaire   +1 more source

Negative-Capacitance FinFET Inverter, Ring Oscillator, SRAM Cell, and Ft

International Electron Devices Meeting, 2018
In this work, we use thermal-ALD to prepare ferroelectric HfZrO2 (HZO) thin film with thickness from 3 to 7 nm for the NC-FinFET's gate stack. The subthreshold swing (SS) was as low as 5 mV/dec (SSmin) over 4 orders of ID.
Kai-Shin Li, Yun-Jie Wei, Yi-Ju Chen, W. Chiu, Hsiu-Chih Chen, Min-Hung Lee, Yu-Fan Chiu, F. Hsueh, Bo-Wei Wu, Pin-Guang Chen, T. Lai, Chun-Chi Chen, J. Shieh, W. Yeh, S. Salahuddin, C. Hu   +15 more
semanticscholar   +1 more source

A Fully Integrated 160Gb/s D-Band Transmitter with 1.1 pJ/b Efficiency in 22nm FinFET Technology

IEEE International Solid-State Circuits Conference, 2022
Increasing demand for data-rate is pushing wireless links to operate at mm-wave (30 to 100GHz) and subTHz (100 to 300GHz) carrier frequencies, where larger available bandwidth can be leveraged to increase capacity.
Steven Callender, A. Whitcombe, Abhishek Agrawal, R. Bhat, Mustafijur Rahman, Chun C. Lee, Peter Sagazio, G. Dogiamis, B. Carlton, Mark Chakravorti, S. Pellerano, C. Hull   +11 more
semanticscholar   +1 more source

A Fully Integrated 160-Gb/s D-Band Transmitter Achieving 1.1-pJ/b Efficiency in 22-nm FinFET

IEEE Journal of Solid-State Circuits, 2022
This work presents a fully integrated 140-GHz transmitter (TX) achieving a data rate of 160 Gb/s with ~1-pJ/b efficiency in the 22-nm Intel FinFET technology.
Steven Callender, Abhishek Agrawal, A. Whitcombe, R. Bhat, Mustafijur Rahman, Chun-Ching Lee, Peter Sagazio, G. Dogiamis, B. Carlton, C. Hull, S. Pellerano   +10 more
semanticscholar   +1 more source

Thermal SPICE Modeling of FinFET and BEOL Considering Frequency-Dependent Transient Response, 3-D Heat Flow, Boundary/Alloy Scattering, and Interfacial Thermal Resistance

IEEE Transactions on Electron Devices, 2019
High device density and high power density intensify the self-heating effect in scaled FinFET circuits to degrade both device and back-end-of-line (BEOL) reliability.
Chia-Che Chung, H. H. Lin, W. K. Wan, M. Yang, Chee-Wee Liu   +4 more
semanticscholar   +1 more source

mmWave and sub-THz Technology Development in Intel 22nm FinFET (22FFL) Process

International Electron Devices Meeting, 2020
This paper presents the recent mmWave and sub-THz oriented technology developments as part of RF design-technology co-optimization (DTCO) efforts in Intel 22nm FinFET process (22FFL).
Q. Yu, S. Rami, J. Waldemer, Yunzhe Ma, V. Neeli, Jeffrey Garrett, Guannan Liu, Jabeom Koo, Mauricio Marulanda, S. Morarka, Surej Ravikumar, Yi-Shin Yeh, Jessica C. Chou, T. Brown, Triveni S. Rane, C. Nieva, D. Ali, S. Joglekar, M. Armstrong, J. Wahl, L. Paulson, G. Dogiamis, Nathan M. Monroe, R. Han, Hyung-Jin Lee, H. Fu, B. Sell, E. Karl, Ying Zhang   +28 more
semanticscholar   +1 more source

15.7 A 32Mb RRAM in a 12nm FinFet Technology with a 0.0249μm2 Bit-Cell, a 3.2GB/S Read Throughput, a 10KCycle Write Endurance and a 10-Year Retention at 105°C

IEEE International Solid-State Circuits Conference
Low-power wireless MCU devices for intelligent IoT applications are one of the key drivers for embedded non-volatile memory (eNVM) for technology nodes of 2xnm and beyond; in addition to high-performance advanced CMOS processes with excellent RF/analog ...
Yi-Cheng Huang, Shang-Hsuan Liu, Hsu-Shun Chen, Hsin-Chang Feng, Chih-Feng Li, Chou-Ying Yang, Wei-Keng Chang, Chang-Feng Yang, Chun-Yu Wu, Yen-Cheng Lin, Tsung-Tse Yang, Chih-Yang Chang, Wen-Ting Chu, H. Chuang, Yih Wang, Y. Chih, T. Chang   +16 more
semanticscholar   +1 more source

A 0.16–3.7GHz Ultra-Compact Noise-Canceling Cryogenic Low-Noise Amplifier at 4 K using 16nm FinFET Technology for Qubit Readout

Device Research Conference
The rapid evolution of quantum computing drives the demand for CMOS cryogenic electronics to support qubit scaling ( Fig. 1 ). In this regard, we present a 16 nm FinFET technology-based cryogenic low noise amplifier (LNA) crucial for enhancing qubit ...
Runzhou Chen, H. Mani, Phil Marsh, R. Hadi, Pragya Shrestha, J. Campbell, Christopher Chen, Hao-Yu Chien, M. F. Chang   +8 more
semanticscholar   +1 more source