Results 41 to 50 of about 134,754 (281)
Software-Level Memory Regulation to Reduce Execution Time Variation on Multicore Real-Time Systems
IEEE Access, 2022 Modern real-time embedded systems are equipped with multi-core processors to execute computationally intensive tasks. In multi-core architecture, last-level cache memory is shared by cores.
Sihyeong Park, Jemin Lee, Hyungshin Kim
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Stochastic Modeling of Hybrid Cache Systems
, 2016 In recent years, there is an increasing demand of big memory systems so to perform large scale data analytics. Since DRAM memories are expensive, some researchers are suggesting to use other memory systems such as non-volatile memory (NVM) technology to ...
Chen, Jiqiang +4 more
core +1 more source
SAMIE-LSQ: set-associative multiple-instruction entry load/store queue [PDF]
, 2006 The load/store queue (LSQ) is one of the most complex parts of contemporary processors. Its latency is critical for the processor performance and it is usually one of the processor hotspots.
Abella Ferrer, Jaume +1 more
core +1 more source
Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs
IEEE Access, 2022 Designs implemented on field-programmable gate arrays (FPGAs) via high-level synthesis (HLS) suffer from off-chip memory latency and bandwidth bottlenecks. FPGAs can access both large but slow off-chip memories (DRAM), and fast but small on-chip memories
Giovanni Brignone +3 more
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LERC: Coordinated Cache Management for Data-Parallel Systems
, 2017 Memory caches are being aggressively used in today's data-parallel frameworks such as Spark, Tez and Storm. By caching input and intermediate data in memory, compute tasks can witness speedup by orders of magnitude.
Letaief, Khaled B. +3 more
core +1 more source
MARACAS: a real-time multicore VCPU scheduling framework [PDF]
, 2016 This paper describes a multicore scheduling and load-balancing framework called MARACAS, to address shared cache and memory bus contention. It builds upon prior work centered around the concept of virtual CPU (VCPU) scheduling.
Cheng, Zhuoqun +3 more
core +1 more source
THE IMPACT ANALYSIS OF PREFETCH IN THE CACHE ON THE MICROPROCESSOR PERFORMANCE
Российский технологический журнал, 2016 Memory access delay has been a major influence on microprocessor systems performance recently. On-chip cache memory application dramatically reduces this delay.
B. Z. Shmeylin
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Striping Input Feature Map Cache for Reducing off-chip Memory Traffic in CNN Accelerators
Telfor Journal, 2020 Data movement between the Convolutional Neural Network (CNN) accelerators and off-chip memory is critical concerning the overall power consumption. Minimizing power consumption is particularly important for low power embedded applications.
R. Struharik, V. Vranjkovic
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Continual Learning for Multimodal Data Fusion of a Soft Gripper
Advanced Robotics Research, EarlyView.Models trained on a single data modality often struggle to generalize when exposed to a different modality. This work introduces a continual learning algorithm capable of incrementally learning different data modalities by leveraging both class‐incremental and domain‐incremental learning scenarios in an artificial environment where labeled data is ...
Nilay Kushawaha, Egidio Falotico
wiley +1 more source
Cache-only memory architectures [PDF]
Computer, 1999 The shared memory concept makes it easier to write parallel programs, but tuning the application to reduce the impact of frequent long latency memory accesses still requires substantial programmer effort. Researchers have proposed using compilers, operating systems, or architectures to improve performance by allocating data close to the processors that
F. Dahlgren, J. Torrellas
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