Results 21 to 30 of about 10,343 (214)

Simulation Model Development for Packaged Cascode Gallium Nitride Field-Effect Transistors

open access: yesCrystals, 2017
This paper presents a simple behavioral model with experimentally extracted parameters for packaged cascode gallium nitride (GaN) field-effect transistors (FETs). This study combined a level-1 metal–oxide–semiconductor field-effect transistor (MOSFET), a
Chih-Chiang Wu, Shyr-Long Jeng
doaj   +1 more source

Recycling folded cascode two-stage CMOS amplifier

open access: yesMemories - Materials, Devices, Circuits and Systems, 2023
In this work, we propose a highly efficient two-stage CMOS amplifier that is based on an improved recycling folded cascode design. The circuit was simulated using TSMC 0.18 μm and HSPICE circuit simulator at a voltage of 1.8 V.
Ilghar Rezaei   +3 more
doaj   +1 more source

High-frequency two-input CMOS OTA for continuous-time filter applications [PDF]

open access: yes, 2000
“This material is presented to ensure timely dissemination of scholarly and technical work. Copyright and all rights therein are retained by authors or by other copyright holders.
Alinii   +15 more
core   +1 more source

A low noise cascode amplifier

open access: yesJournal of Research of the National Bureau of Standards, 1987
We describe the design, schematics, and performance of a very low noise FET cascode input amplifier. This amplifier has noise performance of less than [Formula: see text] and 0.25 [Formula: see text] over the 500 Hz to 50 kHz frequency range. The amplifier is presently being used in conjunction with a Penning ion trap but is applicable to a wide ...
Jefferts, Steven R., Walls, F. L.
openaire   +1 more source

Low voltage cascode amplifier [PDF]

open access: yesThe 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002., 2003
A 0.8 V folded cascode operational amplifier was designed in 0.18 /spl mu/m standard CMOS technology. Emphasis was placed on observing the low voltage design and using a current driven bulk (CDB) technique to achieve this goal. The CDB technique was introduced as a method for low voltage design by reducing the threshold voltage.
Ardalan, Shahab (Author)   +2 more
openaire   +2 more sources

Cascode-based voltage-amplifier stage [PDF]

open access: yesMATEC Web of Conferences, 2017
Voltage-amplifier stages are the basic components of commonly used high gain amplifiers the bias and other parameters of whose are set by the external negative feedback. The typical device that uses the voltage-amplifier stage is the operational amplifier. Similar constructions can also be created on the basis of discrete transistors.
openaire   +3 more sources

Experimental evaluation of medium-voltage cascode gallium nitride (GaN) devices for bidirectional DC-DC converters

open access: yesCES Transactions on Electrical Machines and Systems, 2021
Wide bandgap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), exhibit superior physical properties and demonstrate great potential for replacing conventional silicon (Si) semiconductors with WBG technology, pushing the ...
Salah S. Alharbi, Mohammad Matin
doaj   +1 more source

The BLIXER, a Wideband Balun-LNA-I/Q-Mixer Topology [PDF]

open access: yes, 2008
This paper proposes to merge an I/Q current-commutating mixer with a noise-canceling balun-LNA. To realize a high bandwidth, the real part of the impedance of all RF nodes is kept low, and the voltage gain is not created at RF but in baseband where ...
Blaakmeer, Stephan C.   +3 more
core   +3 more sources

A 2.35/2.4/2.45/2.55 GHz Low-Noise Amplifier Design Using Body Self-Biasing Technique for ISM and LTE Band Application

open access: yesIEEE Access, 2019
This paper presents a quadruple-band low noise amplifier (LNA) which utilizes a differential pair common-source (CS) cascode amplifier to drive a LC-tank loading.
Yen-Chun Wang, Zhe-Yang Huang, Tao Jin
doaj   +1 more source

Offset-compensated comparator with full-input range in 150nm FDSOI CMOS-3d technology [PDF]

open access: yes, 2010
This paper addresses an offset-compensated comparator with full-input range in the 150nm FDSOI CMOS- 3D technology from MIT- Lincoln Laboratory. The comparator discussed here makes part of a vision system.
Brea Sánchez, Víctor Manuel   +5 more
core   +1 more source

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