Results 31 to 40 of about 10,343 (214)
Applied Sciences, 2021 In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and
Gyuri Choi +7 more
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A Breakdown Voltage Multiplier for High Voltage Swing Drivers [PDF]
, 2007 A novel breakdown voltage (BV) multiplier is introduced that makes it possible to generate high output voltage swings using transistors with low breakdown voltages. The timing analysis of the stage is used to optimize its dynamic response.
Hajimiri, Ali, Mandegaran, Sam
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IET Power Electronics, 2022 The utilization of novel cascode GaN devices can significantly increase the power density and the efficiency of convertors. However, owing to high switching speed (high dv/dt or di/dt) and inevitable parasitic inductance in device packages and external ...
Bin Luo, Guangzhao Luo, Sihai Li
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A modular CMOS analog fuzzy controller [PDF]
, 1997 The low/medium precision required for many fuzzy applications makes analog circuits natural candidates to design fuzzy chips with optimum speed/power figures.
Navas González, Rafael +2 more
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IEEE Access, 2020 A novel sub-5-nm node folded cascode structure using dual workfunction (WF) scheme was proposed using fully-calibrated TCAD. Feasible process flows of the cascode device were adopted from those of nanosheet FETs (NSFETs) and complementary FETs.
Jun-Sik Yoon, Rock-Hyun Baek
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A Modular Programmable CMOS Analog Fuzzy Controller Chip [PDF]
, 1999 We present a highly modular fuzzy inference analog CMOS chip architecture with on-chip digital programmability. This chip consists of the interconnection of parameterized instances of two different kind of blocks, namely label blocks and rule blocks. The
Delgado Restituto, Manuel +3 more
core +5 more sources
Global design of analog cells using statistical optimization techniques [PDF]
, 1994 We present a methodology for automated sizing of analog cells using statistical optimization in a simulation based approach. This methodology enables us to design complex analog cells from scratch within reasonable CPU time. Three different specification
Domínguez Castro, Rafael +5 more
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Journal of Low Power Electronics and Applications, 2018 A modified architecture of a comparator to achieve high slew rate and boosted gain with an improvement in gain design error is introduced and investigated in this manuscript.
Anil Khatak, Manoj Kumar, Sanjeev Dhull
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IEEE Journal of the Electron Devices Society, 2023 In this work, the electrical characteristics’ failure due to the chip-level damage and its relationship with the package-level degradation have been investigated for the Cascode GaN device under long-term repetitive power cycling test (PCT).
Yijun Shi +8 more
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Smart-Pixel Cellular Neural Networks in Analog Current-Mode CMOS Technology [PDF]
, 1994 This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels.
Domínguez Castro, Rafael +4 more
core +1 more source