Results 41 to 50 of about 10,343 (214)

Readout Concepts for DEPFET Pixel Arrays [PDF]

, 2002
Field effect transistors embedded into a depleted silicon bulk (DEPFETs) can be used as the first amplifying element for the detection of small signal charges deposited in the bulk by ionizing particles, X-ray photons or visible light.
Fischer, J. Ulrici, Kemmer, Klein, Klein, M. Trimpl, N. Wermes, P. Fischer, Snoeys, Ulrici, W. Neeser   +10 more
core   +3 more sources

Design of a CMOS Power Amplifier With Improved Linearity Through Second-Harmonic Filtering Based on Parasitic Capacitance Analysis

IEEE Journal of Microwaves
In this study, we investigate linearity enhancement of a differential cascode CMOS power amplifier (PA). First, the variation of parasitic capacitance in the common-source (CS) transistor, which directly affects IMD3 and AM-PM distortion, is analyzed as ...
Jiwon Kim, Changhyun Lee, Jinho Yoo, Changkun Park   +3 more
doaj   +1 more source

Design and Evaluation of a 6.5 kV, 400 A Super-Cascode Power Module

IEEE Open Journal of Power Electronics
As the demand for medium-voltage power semiconductors continues to rise, the super-cascode switch has emerged as a promising solution. This paper presents the design, implementation, and experimental evaluation of a 6.5 kV, 400 A super-cascode power ...
Sergio Jimenez, Andrew Lemmon, Arthur Boutry   +2 more
doaj   +1 more source

Gyrator employing field effect transistors [PDF]

, 1973
A gyrator circuit of the conventional configuration of two amplifiers in a circular loop, one producing zero phase shift and the other producing 180 deg phase reversal is examined. All active elements are MOS field effect transistors.
Hochmair, E. S.
core   +1 more source

Study and Analysis of A Simple Self Cascode Regulated Cascode Amplifier

International Journal of Engineering, 2018
This article proposed a simple self cascode RGC amplifier configuration to increase the gain and bandwidth. The cascode amplifier eliminates the miller capacitance between input and output and facilitates high gain, high input and output impedance with high bandwidth.
openaire   +1 more source

An Extended Amplitude Range Readout Circuit for Charged Particle Detection–BEAR 2

Journal of Geophysical Research: Space Physics, Volume 131, Issue 1, January 2026.
Abstract Charge sensitive amplifiers (CSA) form the first stage of most detector readout circuits. The operating range of the readout circuits depends on the saturation limits of the Charge sensitive amplifiers, thereby limiting the range of the detector system as well. A number of methods have been introduced to extend the dynamic range of the readout
A. Antony Gomez, R. W. Knepper, B. M Walsh, S. G. Kanekal, F. Gautier, G. Suarez   +5 more
wiley   +1 more source

Comparison of conventional and cascode drive of SiC BJTs

The Journal of Engineering, 2019
This study compares simple conventional and cascode driver circuits for the SiC bipolar junction transistor (BJT). A low-voltage silicon metal-oxide-semiconductor field-effect transistor is used in the emitter of the BJT to realise the cascode variant ...
Neville McNeill, Mark A. H. Broadmeadow, Nina Roscoe, Stephen Finney   +3 more
doaj   +1 more source

Research on the Synergistic Effect of Total Ionization and Displacement Dose in GaN HEMT Using Neutron and Gamma-Ray Irradiation

Nanomaterials, 2022
This paper studies the synergistic effect of total ionizing dose (TID) and displacement damage dose (DDD) in enhancement-mode GaN high electron mobility transistor (HEMT) based on the p-GaN gate and cascode structure using neutron and 60Co gamma-ray ...
Rui Chen, Yanan Liang, Jianwei Han, Qihong Lu, Qian Chen, Ziyu Wang, Hao Wang, Xuan Wang, Runjie Yuan   +8 more
doaj   +1 more source

Symbolic analysis of large analog integrated circuits by approximation during expression generation [PDF]

, 1994
A novel algorithm is presented that generates approximate symbolic expressions for small-signal characteristics of large analog integrated circuits. The method is based upon the approximation of an expression while it is being computed.
Fernández Fernández, Francisco Vidal, Gièlen, Georges G.E., Rodríguez Vázquez, Ángel Benito, Sansen, Willy M.C., Wambacq, Piet   +4 more
core   +1 more source

Fast‐Locking Frequency‐Hopping PLL Using Dual‐Edge Low‐Duty‐Cycle PFD With Cycle Slip Suppression

IET Circuits, Devices &Systems, Volume 2026, Issue 1, 2026.
The performance of conventional phase–frequency detectors (PFDs) is critically limited by dead‐zone and blind‐zone artifacts, which stem from the timing constraints of D flip‐flop (DFF) based architectures. These non‐idealities degrade phase‐detection resolution, induce cycle slip, and prolong the lock time of phase‐locked loops (PLLs).
Afifeh Ghaemnia, Jincheng Yang, Xiaojiong Fei, Guoqiang Zhang, Paolo Marconcini   +4 more
wiley   +1 more source