Results 51 to 60 of about 10,343 (214)
CMOS design of chaotic oscillators using state variables: a monolithic Chua's circuit [PDF]
, 1993 This paper presents design considerations for monolithic implementation of piecewise-linear (PWL) dynamic systems in CMOS technology. Starting from a review of available CMOS circuit primitives and their respective merits and drawbacks, the paper ...
Delgado Restituto, Manuel +1 more
core +1 more source
Electronics Letters, Volume 62, Issue 1, January/December 2026.This work proposes an adaptive temperature compensation technique to solve the significant temperature dependency of subthreshold analogue front‐ends (AFEs) in low‐power applications. Measurement results from a 180 nm CMOS chip, which utilizes a compact inverter‐based sensor, confirm the technique improves the average SNDR by 4.67 dB at low ...
Jeonghun Lee +4 more
wiley +1 more source
Evaluation of an event‐driven 3FI ASIC for spectroscopic X‐ray detection with synchrotron radiation
Journal of Synchrotron Radiation, Volume 33, Issue 1, Page 154-161, January 2026.A new event‐driven, energy‐resolving ASIC intended for full‐field X‐ray fluorescence imaging is presented. Its frameless mode of operation was validated on a synchrotron beamline using a bump‐bonded, 2D segmented silicon sensor, demonstrating per‐pixel energy measurements with event‐driven readout.
Piotr Maj +12 more
wiley +1 more source
IEEE Open Journal of Circuits and Systems, 2023 In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode ...
Milad Haghi Kashani +2 more
doaj +1 more source
High Gain Amplifier with Enhanced Cascoded Compensation [PDF]
, 2014 A two-stage CMOS operational amplifier with both, gain-boosting and indirect current feedback frequency compensation performed by means of regulated cascode amplifiers, is presented. By using quasi-floating-gate transistors (QFGT) the supply requirements,
Diaz-Sanchez, A. +5 more
core +1 more source
CMOS mixed-signal MODEM for data transmission and control of electrical household appliances using the low-voltage power-line [PDF]
, 2003 This paper presents a CMOS 0.6μm mixed-signal MODEM ASIC for data transmission using the low-voltage power line. This circuit includes all the analog blocks needed for input interfacing and modulation/demodulation (PLL-based frequency synthesis, slave ...
Domínguez Matas, Carlos +4 more
core +1 more source
Linear cascode current-mode integrator [PDF]
The Journal of the Korea institute of electronic communication sciences, 2013 This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency.
Byoung-Wook Kim, Dae-Ik Kim
openaire +1 more source
Reversed Nested Miller‐Based Four Stage CMOS Amplifier Frequency Compensation Approach
Active and Passive Electronic Components, Volume 2026, Issue 1, 2026.This work presents a novel frequency compensation method for four‐stage CMOS amplifiers, addressing the complexity and instability challenges prevalent in modern low‐voltage, low‐power electronic systems. The proposed approach employs nested differential gain stages combined with a single, compact Miller capacitor at the common output, which enables ...
Marziyeh Raofi Moghadam +2 more
wiley +1 more source
A 24-GHz, +14.5-dBm fully integrated power amplifier in 0.18-μm CMOS [PDF]
, 2005 A 24-GHz +14.5-dBm fully integrated power amplifier with on-chip 50-[ohm] input and output matching is demonstrated in 0.18-μm CMOS. The use of substrate-shielded coplanar waveguide structures for matching networks results in low passive loss and small ...
Hajimiri, Ali +2 more
core
A Scalable 6-to-18 GHz Concurrent Dual-Band Quad-Beam Phased-Array Receiver in CMOS [PDF]
, 2008 This paper reports a 6-to-18 GHz integrated phased- array receiver implemented in 130-nm CMOS. The receiver is easily scalable to build a very large-scale phased-array system. It concurrently forms four independent beams at two different frequencies from
Babakhani, Aydin +6 more
core +3 more sources