Results 241 to 250 of about 54,421 (264)

MicroSMD-a wafer level chip scale package

IEEE Transactions on Advanced Packaging, 2000
exaly  

Chip Package Interaction (CPI) risk assessment of 22FDX® Wafer Level Chip Scale Package (WLCSP) using 2D Finite Element Analysis modeling

2020
Frank Kuechenmeister, Kashi Vishwanath Machani, Dirk Breuer   +2 more
exaly  

Mechanical strength of chip scale package with various underfills under accelerated thermal condition

Materials Science and Technology, 2007
exaly  

Capability evaluation and validation of FC chip scale package structure

2011
Eason Chen
exaly  

Chip scale package of a MEMS microphone and ASIC stack

2010
Gregor Feiertag, Helmut Seidel, Anton Leidl   +2 more
exaly  

Development of a Low CTE chip scale package

2013
Kenji Terada
exaly  

OVERMOLDED CHIP SCALE PACKAGE

2017
BURMEISTER FRANK, LEUNG CHI HO, LI ZHIGANG, ZHAO YUNJUN, KIRCHHEIMER KAREN, RITTER HANS-MARTIN   +5 more
openaire   +1 more source

Structure and manufacturing method of chip scale package

2012
LIN MOU-SHIUNG, LEI MING-TA, LIN CHUEN-JYE   +2 more
openaire   +3 more sources

AMKOR expands stacked chip-scale package capacity and 3D packaging family

Microelectronics International, 2000
exaly  

Ultra-dense silicon photonics optical IO solution for optical chip scale package

2016
Xiaolu Song
exaly