Results 231 to 240 of about 54,421 (264)

Panel-Level Chip-Scale Package With Multiple Diced Wafers

IEEE Transactions on Components, Packaging and Manufacturing Technology, 2020
Eagle Lin, Kai Ming Yang, John Lau
exaly  

Chip Scale Packaging for Modern Electronics

Soldering & Surface Mount Technology, 2004
  +4 more sources

Thermal stress analysis and design optimization of direct chip attach (DCA) and chip scale package (CSP) in flip chip technology

Engineering Optimization, 2002
D S Liu
exaly  

The Chip Scale Package

2007
openaire   +1 more source

Thermal fatigue performance of Sn–Ag–Cu chip-scale package with underfill

Materials Science & Engineering A: Structural Materials: Properties, Microstructure and Processing, 2008
Seung-Boo Jung, Bo-In Noh, Bo-Young Lee   +2 more
exaly  

On-Chip High-$Q$Variable Inductor Using Wafer-Level Chip-Scale Package Technology

IEEE Transactions on Electron Devices, 2006
Kazuya Masu, K Itoi
exaly  

Molded chip scale package for high pin count

IEEE Transactions on Advanced Packaging, 1998
H Matsushima
exaly  

Thermal resistance and optical performance of SMD LEDs with traditional package and chip scale package

2021
exaly  

Chip scale package: ‘a lightly dressed LSI chip’

Microelectronics Reliability, 1997
openaire   +1 more source

Numerical analysis on thermal characteristics for chip scale package by integrating 2D/3D models

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, 2009

exaly