Results 291 to 300 of about 1,091,701 (330)

9.5 An 80Gb/s 300GHz-Band Single-Chip CMOS Transceiver

IEEE International Solid-State Circuits Conference, 2019
IEEE Standard 802.15.3d, published in October 2017, defines a high-data-rate wireless physical layer that enables up to 100Gb/s using the lower THz frequency range between 252 and 325GHz (hereafter referred to as the “300GHz band”).
Sangyeop Lee, R. Dong, T. Yoshida, S. Amakawa, S. Hara, A. Kasamatsu, J. Sato, M. Fujishima   +7 more
semanticscholar   +1 more source

An object-oriented design paradigm for standard CMOS fabrication technology

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), 2003
The object-oriented design methodology has been manipulated to model the standard CMOS fabrication technology. Detecting and characterizing the objects and classes within the basic object-oriented features of encapsulation, inheritance and polymorphism, as well as discussing the model framework and model characterization has been the main pursuits of ...
B. Hekmatshoar, C. Lucas
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Watermark induced High Density Via failures in sub micron CMOS fabrication

2006 IEEE International Symposium on Semiconductor Manufacturing, 2006
High via resistance was detected in the high density via structure in our 0.15 mum BEOL (Back-End-Of-Line) yield monitoring test vehicle. A localized insulating layer was found on top of plug in test vehicle causing high via resistance. The failure was attributed to watermark induced contaminants on top of the W plug.
Alex Chew, H.H. Au, S.H. Han, T.L. Neo, Jackson Tan, K.W. Chai, Samuel Chua   +6 more
openaire   +1 more source

Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Graphene is an emerging nano-material that has garnered immense research interest due to its exotic electrical properties. It is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability.
Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz   +5 more
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Towards a framework for designing applications onto hybrid nano/CMOS fabrics

Microelectronics Journal, 2009
The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics.
Dezan, Catherine, Teodorov, Ciprian, Lagadec, Loïc, Leuchtenburg, Michael, Wang, Teng, Narayanan, Pritish, Moritz, Csaba Andras   +6 more
openaire   +2 more sources

A Full Ka-Band Power Amplifier With 32.9% PAE and 15.3-dBm Power in 65-nm CMOS

IEEE Transactions on Circuits and Systems Part 1: Regular Papers, 2018
This paper presents a CMOS broadband millimeter wave power amplifier (PA) based on magnetically coupled resonator (MCR) matching network. The MCR matching network is analyzed theoretically. Design method for MCR-based broadband PA is proposed. For the PA’
Haikun Jia, Clarissa C. Prawoto, B. Chi, Zhihua Wang, C. Yue   +4 more
semanticscholar   +1 more source

Low-loss integrated ring-resonator filters realized by CMOS fabrication process

2017 Conference on Lasers and Electro-Optics Europe & European Quantum Electronics Conference (CLEO/Europe-EQEC), 2017
During the last decade Silicon photonics emerged as mature technology in the field of integrated optics for the fabrication of low-cost optical integrated circuits [1]. Silicon-on-insulator (SOI) represents the ideal platform for the realization of optical circuits characterized by a strong optical confinement, because of the large index contrast ...
R. Marchetti, V. Vitali, C. Lacava, I. Cristiani, G. Giuliani, L. Adelmini, M. Fournier, P. Minzioni   +7 more
openaire   +1 more source

SiGe CMOS fabrication using SiGe MBE and anodic/LTO gate oxide

Semiconductor Science and Technology, 2000
An investigation of an SiGe CMOS process fulfilling low-thermal-budget requirements was carried out. Three different undoped layers were grown successively by MBE: a 20 nm buffer layer, a 15 nm SiGe layer and a 15 nm cap layer. The Ge concentration of the SiGe layer was either uniform 20% or linearly graded 0-40% from the substrate to the surface. A 50
Sidek, R M, Straube, U N, Waite, A M, Evans, A G R, Parry, C, Phillips, P, Whall, T E, Parker, E H C   +7 more
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The defects analysis in CMOS fabrication by arrhenius activation energy technique

2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011
Low power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the ...
Weera Pengchan, Toempong Phetchakul, Amporn Poyai   +2 more
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Developments in 300mm silicon photonics using traditional CMOS fabrication methods and materials

2017 IEEE International Electron Devices Meeting (IEDM), 2017
Silicon photonics technological platforms are meant to generate derivative products and concurrently to benefit from the main advantages associated with CMOS platforms namely: high yield, system robustness, product reliability and large volume, low cost production.
Baudot, C., Douix, M., Guerber, S., Cremer, S., Vulliet, N., Planchot, J., Blanc, R., Babaud, L., Alonso-Ramos, C., Benedikovich, D., Perez-Galacho, D., Messaoudene, S., Kerdiles, S., Acosta-Alba, P., Euvrard-Colnat, C., Cassan, E., Marris-Morini, D., Vivien, L., Boeuf, F.   +18 more
openaire   +1 more source