Results 271 to 280 of about 418,483 (315)

Nanotechnology in Silicon CMOS Fabrication

ECS Meeting Abstracts, 2008
Abstract not Available.
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NWELL CMOS fabrication process for the Virginia Microelectronics Center

Proceedings of the Fourteenth Biennial University/Government/Industry Microelectronics Symposium (Cat. No.01CH37197), 2002
The VMC is developing a CMOS process to help teach microelectronics students the techniques of semiconductor fabrication. It is also intended to be a vehicle for the implementation of VLSI digital and analog circuit designs at VCU. The development of the CMOS process is an on-going senior electrical engineering project.
N.R. Balderson, G. Cordova, null Kwang Yi, A. Guliani, S. Manek, G.W. Schiavone, J. Harrison, R.E. Pearson   +7 more
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Thermoelectric power sensor for microwave applications by commercial CMOS fabrication

IEEE Electron Device Letters, 1997
This work describes an implementation of a thermoelectric microwave power sensor fabricated through commercial CMOS process with additional maskless etching. The sensor combines micromachined coplanar waveguide and contact pads, a microwave termination which dissipates heat proportionally to input microwave power, and many aluminum-polysilicon ...
V. Milanovic, M. Gaitan, E.D. Bowen, N.H. Tea, M.E. Zaghloul   +4 more
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Modeling and Characterization of CMOS-Fabricated Capacitive Micromachined Ultrasound Transducers

Journal of Microelectromechanical Systems, 2011
This paper describes the fabrication, characterization, and modeling of complementary metal-oxide-semiconductor (CMOS)-compatible capacitive micromachined ultrasound transducers (CMUTs). The transducers are fabricated using the interconnect and dielectric layers from a standard CMOS fabrication process.
Christopher B. Doody, Xiaoyang Cheng, Collin A. Rich, David F. Lemmerhirt, Robert D. White   +4 more
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Commercial CMOS fabricated integrated dynamic thermal scene simulator

International Electron Devices Meeting 1991 [Technical Digest], 2002
The authors report a prototype integrated dynamic thermal scene simulator chip, consisting of a 2*2 array of integrated thermal pixels. The chips were fabricated using commercial CMOS processes. The micromachining process needed to create the thermally isolated structure is introduced as a maskless postprocessing step. The thermal pixel and the control
M. Parameswaran, R. Chung, M. Gaitan, R.B. Johnson, M. Syrzycki   +4 more
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Ternary volatile random access memory based on heterogeneous graphene-CMOS fabric

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012
Graphene is an emerging nano-material that has garnered immense research interest due to its exotic electrical properties. It is believed to be a potential candidate for post-Si nanoelectronics due to high carrier mobility and extreme scalability.
Santosh Khasanvis, K. M. Masum Habib, Mostafizur Rahman, Pritish Narayanan, Roger K. Lake, Csaba Andras Moritz   +5 more
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An object-oriented design paradigm for standard CMOS fabrication technology

Proceedings of the 12th IEEE International Conference on Fuzzy Systems (Cat. No.03CH37442), 2003
The object-oriented design methodology has been manipulated to model the standard CMOS fabrication technology. Detecting and characterizing the objects and classes within the basic object-oriented features of encapsulation, inheritance and polymorphism, as well as discussing the model framework and model characterization has been the main pursuits of ...
B. Hekmatshoar, C. Lucas
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High performance CMOS fabricated on hybrid substrate with different crystal orientations

IEEE International Electron Devices Meeting 2003, 2004
A novel structure and technology has been developed for high performance CMOS using hybrid silicon substrates with different crystal orientations (namely pFET on [110]-oriented surface and nFET on (100) surface) through wafer bonding and selective epitaxy.
M. Yang, M. Ieong, L. Shi, K. Chan, V. Chan, A. Chou, E. Gusev, K. Jenkins, D. Boyd, Y. Ninomiya, D. Pendleton, Y. Surpris, D. Heenan, J. Ott, K. Guarini, C. D'Emic, M. Cobb, P. Mooney, B. To, N. Rovedo, J. Benedict, R. Mo, H. Ng   +22 more
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Submicrometer poly-Si CMOS fabrication with low-temperature laser doping

IEEE Electron Device Letters, 1989
The laser doping process for submicrometer CMOS devices with leakage currents as low as 10/sup -12/ A/ mu m for both n-channel and p-channel devices is discussed. The I-V characteristics are comparable to those of poly-Si devices fabricated using ion implantation and high-temperature annealing processes.
H. Tomita, M. Negishi, T. Sameshima, S. Usui   +3 more
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Understanding clustering of defects in a sub-0.5 μm CMOS fabricator

Proceedings International Conference on Microelectronic Test Structures, 2002
Over two decades of bipolar-experience has previously alerted one to the fact that the extent of defect clustering, assumed in the CMOS yield models, may not hold for defects monitored on microelectronic test structures (MTS). Tracing the defect clustering from inline CMOS MTS, we now describe a viable yield prediction model using data from the various
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