Results 261 to 270 of about 418,483 (315)

Nanotechnology in Silicon CMOS Fabrication and Nanoelectronics

7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2006
Summary form only given. While novel device structures using nanomaterials such as carbon nanotubes and organic molecules may be far away, there are opportunities to use nanomaterials in solving critical issues faced by silicon CMOS downscaling. Two examples, both using carbon nanotubes, in chip cooling and developing interconnects were discussed ...
A. Cassell, null Jun Li, null Quoc Ngo, C. Nguyen, null Bin Yu, M. Meyyappan   +5 more
openaire   +1 more source

Multijunction thermal converters by commerical CMOS fabrication

1993 IEEE Instrumentation and Measurement Technology Conference, 2002
New multijunction thermal converters (MJTCs) fabricated in a commerical CMOS foundry are described. The MJTC is a cantilever structure with a suspended, resistance heating element and thermocouple hot junctions located near the heater on the cantilever. The pit etched below is 150 /spl times/ 150 /spl mu/m in size. The heater structure is composed of a
M. Gaitan, J. Suehle, J.R. Kinard, D.X. Huang   +3 more
openaire   +1 more source

Process simplification in deep submicron CMOS fabrication

Proceedings of International Symposium on Semiconductor Manufacturing, 2002
Process simplification in deep submicron CMOS fabrication is discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation process are extracted as items to simplify the process. A combination of shallow trench isolation and single mask step well/gate doping is proposed for
H. Koike, H. Ohtsuka, F. Matsuoka, M. Kakumu, K. Maeguchi   +4 more
openaire   +1 more source

Defect cluster segmentation for CMOS fabricated wafers

2009 Innovative Technologies in Intelligent Systems and Industrial Applications, 2009
IC defects, which are essentially present in all fabricated wafers, can either be random defects or belonging to a group of systematic defects. The ability to segment systematic defects that are present in a wafer allows rapid root cause identification and corrective measures to be taken.
W.J. Tee, M.P-L. Ooi, Y.C. Kuang, C. Chan   +3 more
openaire   +1 more source

CMOS Fabricated by Hybrid-Orientation Technology (HOT)

2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007
Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence ...
Bin Yang, M. Yang, D. M. Fried, C. D. Sheraw, A. Waite, K. Nummy, L. Black, S. D. Kim, H. Yin, B. Kim, S. Narasimha, X. Chen, M. Khare, S. Luning, P. Agnello   +14 more
openaire   +1 more source

The defects analysis in CMOS fabrication by arrhenius activation energy technique

2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011
Low power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the ...
W. Pengchan, T. Phetchakul, A. Poyai
openaire   +1 more source

Process development for CMOS fabrication using minimal fab

2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 2017
CMOS fabrication processes based on clean-localized technology of Minimal fab are introduced in this work. Without a cleanroom, the particle and impurities are locally controlled at each machine and wafer carrier during the fabrication process. Two methods of CMOS inverter fabrication are performed, 1) using only equipment of a minimal fab for entire ...
Sommawan Khumpuang, Kazuhiro Koga, Yongxun Liu, Shiro Kara   +3 more
openaire   +1 more source

Micromachined microwave transmission lines by commercial CMOS fabrication

Proceedings of the 39th Midwest Symposium on Circuits and Systems, 2002
Coplanar waveguides were designed and fabricated in standard CMOS with post-processing micromachining. Transmission line layouts were designed with commercial CAD tools, ICs were fabricated through a commercial CMOS foundry, and subsequently suspended by maskless top-side etching.
V. Milanovic, M. Gaitan, E.D. Bowen, M.E. Zaghloul   +3 more
openaire   +1 more source

Micromachined thermocouple microwave detector by commercial CMOS fabrication

IEEE Transactions on Microwave Theory and Techniques, 1998
This paper reports on the design and testing of a thermocouple microwave detector fabricated through a commercial CMOS foundry with an additional maskless etching procedure. The detector measures true r.m.s. power of signals in the frequency range from 50 MHz to 20 GHz, and input power range from -30 to +10 dBm, the device has linearity better than ...
V. Milanovic, M. Gaitan, M.E. Zaghloul
openaire   +1 more source

Towards a framework for designing applications onto hybrid nano/CMOS fabrics

Microelectronics Journal, 2009
The design of CAD tools for nanofabrics involves new challenges not encountered with conventional design flow used for CMOS technology. In this paper, we propose to define a new framework able to help the designer to map an application on a wide range of emerging nanofabrics.
Catherine Dezan, Ciprian Teodorov, Loïc Lagadec, Michael Leuchtenburg, Teng Wang, Pritish Narayanan, Csaba Andras Moritz   +6 more
openaire   +2 more sources