Results 241 to 250 of about 537,942 (300)

Nanotechnology in Silicon CMOS Fabrication and Nanoelectronics

7th. Int. Conf. on Thermal, Mechanical and Multiphysics Simulation and Experiments in Micro-Electronics and Micro-Systems, 2006
Summary form only given. While novel device structures using nanomaterials such as carbon nanotubes and organic molecules may be far away, there are opportunities to use nanomaterials in solving critical issues faced by silicon CMOS downscaling. Two examples, both using carbon nanotubes, in chip cooling and developing interconnects were discussed ...
A. Cassell, null Jun Li, null Quoc Ngo, C. Nguyen, null Bin Yu, M. Meyyappan   +5 more
openaire   +1 more source

Optical characteristics of CMOS-fabricated MOSFET's

IEEE Journal of Solid-State Circuits, 1987
A CMOS fabricated MOSFET in a floating p-well on a semiconducting n-type substrate is optically sensitive and can be used for photoreception in CMOS circuitry. Experimental results for the logarithmic dependence of threshold voltage V/SUB th/ and channel current I/SUB D/ on light intensity compare well with the theory. However, the floating p-well also
Kirkish, S. D., Daly, J. C., Jou, L., Su, Shing Fong   +3 more
openaire   +2 more sources

Multijunction thermal converters by commerical CMOS fabrication

1993 IEEE Instrumentation and Measurement Technology Conference, 2002
New multijunction thermal converters (MJTCs) fabricated in a commerical CMOS foundry are described. The MJTC is a cantilever structure with a suspended, resistance heating element and thermocouple hot junctions located near the heater on the cantilever. The pit etched below is 150 /spl times/ 150 /spl mu/m in size. The heater structure is composed of a
M. Gaitan, J. Suehle, J.R. Kinard, D.X. Huang   +3 more
openaire   +1 more source

CMOS-Fabricated Ring Surface Ion Trap with TSV Integration

2023 International Electron Devices Meeting (IEDM), 2023
We present the design, fabrication, and test of ring surface trap on 12-inch wafers with a CMOS process. The design is based on Through Silicon Vias (TSV) interconnects. Up to 200 ions were loaded and cooled; preliminary compensations of electrostatic potential imperfections show that rotational symmetry can be partially restored.
Zhao, Peng, Lim, Yu Dian, Li, Hongyu, Likforman, Jean-Pierre, Guidoni, Luca, Desormeaux, Lilay Gros, Tan, Chuan Seng   +6 more
openaire   +2 more sources

Process simplification in deep submicron CMOS fabrication

Proceedings of International Symposium on Semiconductor Manufacturing, 2002
Process simplification in deep submicron CMOS fabrication is discussed. Process step analysis is carried out for standard 1Poly/1Metal CMOS structure, and consequently, both isolation and gate formation process are extracted as items to simplify the process. A combination of shallow trench isolation and single mask step well/gate doping is proposed for
H. Koike, H. Ohtsuka, F. Matsuoka, M. Kakumu, K. Maeguchi   +4 more
openaire   +1 more source

Defect cluster segmentation for CMOS fabricated wafers

2009 Innovative Technologies in Intelligent Systems and Industrial Applications, 2009
IC defects, which are essentially present in all fabricated wafers, can either be random defects or belonging to a group of systematic defects. The ability to segment systematic defects that are present in a wafer allows rapid root cause identification and corrective measures to be taken.
W.J. Tee, M.P-L. Ooi, Y.C. Kuang, C. Chan   +3 more
openaire   +1 more source

Nanotechnology in Silicon CMOS Fabrication

ECS Meeting Abstracts, 2008
Abstract not Available.
openaire   +1 more source

CMOS Fabricated by Hybrid-Orientation Technology (HOT)

2007 International Workshop on Electron Devices and Semiconductor Technology (EDST), 2007
Hybrid-orientation technology (HOT), a novel planar CMOS approach that fabricates NMOS on (100) silicon surface and PMOS on (110) silicon surface to take advantage of the highest carrier mobilities on these surfaces, is reviewed. HOT module process flow, defects formed during the HOT module, HOT CMOS performance enhancement and its layout dependence ...
Bin Yang, M. Yang, D. M. Fried, C. D. Sheraw, A. Waite, K. Nummy, L. Black, S. D. Kim, H. Yin, B. Kim, S. Narasimha, X. Chen, M. Khare, S. Luning, P. Agnello   +14 more
openaire   +1 more source

The defects analysis in CMOS fabrication by arrhenius activation energy technique

2011 6th IEEE International Conference on Nano/Micro Engineered and Molecular Systems, 2011
Low power consumption device can be realized by low junction leakage current. This leakage current relates to the defects in the depletion region of p-n junction. Among variety process steps, implantation step may generate defects. Therefore, the implantation-induced defects have been studied from the activation energy which has been obtained from the ...
W. Pengchan, T. Phetchakul, A. Poyai
openaire   +2 more sources

Process development for CMOS fabrication using minimal fab

2017 IEEE Electron Devices Technology and Manufacturing Conference (EDTM), 2017
CMOS fabrication processes based on clean-localized technology of Minimal fab are introduced in this work. Without a cleanroom, the particle and impurities are locally controlled at each machine and wafer carrier during the fabrication process. Two methods of CMOS inverter fabrication are performed, 1) using only equipment of a minimal fab for entire ...
Sommawan Khumpuang, Kazuhiro Koga, Yongxun Liu, Shiro Kara   +3 more
openaire   +1 more source