Results 281 to 290 of about 418,483 (315)

A New Approach for CMOS Fabrication of Microcantilever/Nanotip Systems for Probe-Storage Applications

2009
A novel method for fabricating the mechanical part of the “Millipede”, a MEMS-based scanning-probe data storage system, is reported. The proposed approach exploits a selective p-to-n HF-based electropolishing step, which allows to remove p-type silicon, used as a sacrificial layer, while leaving n-type silicon, exploited as structural material, un ...
BARILLARO, GIUSEPPE, SURDO, SALVATORE, Lazzerini G. M.   +2 more
openaire   +1 more source

Process Characterization and Control of Polycrystalline SiGe as the Gate Electrode in CMOS Fabrication

Journal of The Electrochemical Society, 2005
Polycrystalline Si 1 - x Ge x (poly-SiGe) films have been proposed as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal-oxide-semiconductor (CMOS) field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion than that of poly-Si ...
Hong Lin, Wai Lo, Shiqun Gu, Verne Hornback, Jim Elmer, Wilbur Catabay   +5 more
openaire   +1 more source

A novel capacitive-type humidity sensor using CMOS fabrication technology

Sensors and Actuators B: Chemical, 2004
Abstract This paper reports a novel capacitive humidity sensor integrated on a polysilicon heater. The sensor was fabricated with the industrial standard CMOS process to achieve a cost-effective solution for accurate and reliability. The sensing material polyimide was obtained by a post-processing step after the standard CMOS fabrication. The sensing
Lei Gu, Qing-An Huang, Ming Qin
openaire   +1 more source

CMOS-fabricated tensile Ge microstructures: towards an edge-emitting laser

2014 7th International Silicon-Germanium Technology and Device Meeting (ISTDM), 2014
The realization of a Si-integrated light source represents today the "Holy Grail" of silicon photonics. An approach based on slightly tensile strained Ge/Si heterostructures has led to the demonstration of both optically and electrically pumped laser.
CAPELLINI, GIOVANNI, Reich C, Guha S, Yamamoto Y, Lischke S, Kreissl J, Zimmermann L, Virgilio M, Ghrib A, El Kurdi M, Boucaud P, Tillack B, Schroeder T.   +12 more
openaire   +1 more source

Subnanometer Linewidth Uniformity in Silicon Nanophotonic Waveguide Devices Using CMOS Fabrication Technology

IEEE Journal of Selected Topics in Quantum Electronics, 2010
We report subnanometer linewidth uniformity in silicon nanophotonics devices fabricated using high-volume CMOS fabrication tools. We use wavelength-selective devices such as ring resonators, Mach-Zehnder interferometers, and arrayed waveguide gratings to assess the device nonuniformity within and between chips.
Selvaraja S.K., Bogaerts W., Dumon P., Van Thourhout D., Baets R.   +4 more
openaire   +1 more source

Watermark induced High Density Via failures in sub micron CMOS fabrication

2006 IEEE International Symposium on Semiconductor Manufacturing, 2006
High via resistance was detected in the high density via structure in our 0.15 mum BEOL (Back-End-Of-Line) yield monitoring test vehicle. A localized insulating layer was found on top of plug in test vehicle causing high via resistance. The failure was attributed to watermark induced contaminants on top of the W plug.
Alex Chew, H.H. Au, S.H. Han, T.L. Neo, Jackson Tan, K.W. Chai, Samuel Chua   +6 more
openaire   +1 more source

Critical need and future directions of SIMS depth profiling in CMOS fabrication

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2018
The complementary metal-oxide-semiconductor (CMOS) industry continues to push the boundaries of what is possible. Along with this, secondary ion mass spectrometry (SIMS) depth profiling continues to support CMOS R&D and high volume manufacturing (due to its unparalleled sensitivity and detection limits over predefined volumes and within acceptable ...
openaire   +1 more source

On the Two-Step Nucleation in Internal Gettering for CMOS Fabrication Process

Solid State Phenomena, 1989
J. Jablonski, K. Kucharski, J. Wojciechowski   +2 more
openaire   +1 more source

The temperature characteristics of bipolar transistors fabricated in CMOS technology

Sensors and Actuators A: Physical, 2000
Gérard C M Meijer
exaly  

CMOS Fabrication

2006
openaire   +1 more source