Results 301 to 310 of about 1,091,701 (330)

High-performance CMOS fabricated on ultrathin BESOI with sub-10 nm ttv

Proceedings of 1993 IEEE International SOI Conference, 2002
Ultra thin Bond and Etch-back Silicon On Insulator (BESOI) in the thickness range of 75 to 100 nn offers the potential for performance enhancement in both CMOS and BiCMOS technology. To be useful, however, a very low total thickness variation (ttv) is desirable, typically below 10 nm.
S.S. Iyer, M.J. Tejwani, P.M. Pitner, T.O. Sedgwick, G.G. Shahidi   +4 more
openaire   +1 more source

Watermark-Induced High-Density Via Failures in Submicron CMOS Fabrication (May 2006)

IEEE Transactions on Semiconductor Manufacturing, 2007
High via resistance was detected in the high-density via structure in our 0.15-mum back-end-of-line (BEOL) yield monitoring test vehicle. A localized insulating layer was found on top of the plug in test vehicle causing high via resistance. The failure was attributed to watermark-induced contaminants on top of the W plug.
Alex Chew, Hing Ho Au, S. H. Han, T. L. Neo, Jackson Tan, K. W. Chai, Samuel Chua   +6 more
openaire   +1 more source

Understanding clustering of defects in a sub-0.5 μm CMOS fabricator

Proceedings International Conference on Microelectronic Test Structures, 2002
Over two decades of bipolar-experience has previously alerted one to the fact that the extent of defect clustering, assumed in the CMOS yield models, may not hold for defects monitored on microelectronic test structures (MTS). Tracing the defect clustering from inline CMOS MTS, we now describe a viable yield prediction model using data from the various
openaire   +1 more source

A cryo-CMOS chip that integrates silicon quantum dots and multiplexed dispersive readout electronics

Nature Electronics, 2021
A. Ruffino, Tsung-Yeh Yang, J. Michniewicz, Yatao Peng, E. Charbon, M. Gonzalez-Zalba   +5 more
semanticscholar   +1 more source

Critical need and future directions of SIMS depth profiling in CMOS fabrication

Journal of Vacuum Science & Technology B, Nanotechnology and Microelectronics: Materials, Processing, Measurement, and Phenomena, 2018
The complementary metal-oxide-semiconductor (CMOS) industry continues to push the boundaries of what is possible. Along with this, secondary ion mass spectrometry (SIMS) depth profiling continues to support CMOS R&D and high volume manufacturing (due to its unparalleled sensitivity and detection limits over predefined volumes and within acceptable ...
openaire   +1 more source

A high-speed programmable and scalable terahertz holographic metasurface based on tiled CMOS chips

Nature Electronics, 2020
S. Venkatesh, Xuyang Lu, H. Saeidi, K. Sengupta   +3 more
semanticscholar   +1 more source

Theoretical and Experimental Investigations of Thermoresistive Micro Calorimetric Flow Sensors Fabricated by CMOS MEMS Technology

Journal of microelectromechanical systems, 2016
Wei Xu, Kui Song, Shenhui Ma, Bo Gao, Y. Chiu, Yi-Kuen Lee   +5 more
semanticscholar   +1 more source

Area-Dependent Photodetection Frequency Response Characterization of Silicon Avalanche Photodetectors Fabricated With Standard CMOS Technology

IEEE Transactions on Electron Devices, 2013
Myung-Jae Lee, W. Choi
semanticscholar   +1 more source

A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology

IEEE Journal of Solid-State Circuits, 2012
M. Gersbach, Y. Maruyama, Rahmadi Trimananda, M. Fishburn, D. Stoppa, J. Richardson, R. Walker, R. Henderson, E. Charbon   +8 more
semanticscholar   +1 more source

Effects of Guard-Ring Structures on the Performance of Silicon Avalanche Photodetectors Fabricated With Standard CMOS Technology

IEEE Electron Device Letters, 2012
Myung-Jae Lee, H. Rucker, W. Choi
semanticscholar   +1 more source