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ST-CMOS (Stacked Transistors CMOS): A double-poly-NMOS-compatible CMOS technology
1981 International Electron Devices Meeting, 1981A modified double-poly NMOS technology is proposed, providing CMOS structures. The P-channel transistors are made in the second poly layer. The process scheme is standard, except for the laser annealing step. A method of laser annealing of processed [even non-planar] samples is derived, giving rise to a concept of selective annealing.
J.P. Colinge, E. Demoulin
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Graphene for CMOS and Beyond CMOS Applications
Proceedings of the IEEE, 2010Owing in part to complementary metal-oxide-semiconductor (CMOS) scaling issues, the semiconductor industry is placing an increased emphasis on emerging materials and devices that may provide a solution beyond the 22-nm node. Single and few layers of carbon sheets (graphene) have been fabricated by a variety of techniques including mechanical ...
Sanjay K. Banerjee +6 more
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Adiabatic-CMOS/CMOS-adiabatic logic interface circuit
International Journal of Electronics, 2000This paper describes the design of an adiabatic-CMOS/CMOS-adiabatic logic interface circuit for a group of low-power adiabatic logic families with a similar clocking scheme. The circuit provides interfacing between several recently proposed low-power adiabatic logic circuits and traditional digital CMOS circuits. One advantage of this design is that it
K. T. Lau, W. Y. Wang, K. W. Ng
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Pulsed power supply CMOS-PPS CMOS
Proceedings of 1994 IEEE Symposium on Low Power Electronics, 2002Low power dissipation using conventional CMOS circuits can be achieved if the power supply lead is ramped repetitively between VDD and VSS. During the power-down edge, the state of the chip is stored on parasitic capacitances. This quasi-static CMOS circuit technique is called PPS (Pulsed Power Supply) CMOS and reduces the power dissipation over ...
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CMOS is dead … long live CMOS!
2007 IEEE Hot Chips 19 Symposium (HCS), 2007This article consists of a collection of slides from the author's conference presentation on the future of CMOS technologies. Some of the specific topics discussed include: the market for CMOS scaling; design considerations for materials plus CMOS scaling; the future that considers devices plus materials plus CMOS scaling; and new areas of future chip ...
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Alternative CMOS or alternative to CMOS?
Microelectronics Reliability, 2001Abstract We point out the main issues to address in order to investigate and push the limits of CMOS technology. The demand for low voltage, low power and high performance are the great challenges for engineering of sub-0.10 μm gate length devices. The possible solutions are reviewed through the issues in gate/channel and substrate, source and drain ...
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Molecular Approach to Engineer Two-Dimensional Devices for CMOS and beyond-CMOS Applications
Chemical Reviews, 2022Yuda Zhao, Marco Gobbi, Luis E Hueso
exaly