Results 81 to 90 of about 644,668 (339)
On optimal structure and geometry of high-speed integrated photodiodes in a standard CMOS technology [PDF]
Analyses of the influence of different geometries (layouts) and structures of high-speed CMOS photodiodes on their intrinsic (physical) and electrical bandwidths are presented.
Annema, Anne-Johan +2 more
core +2 more sources
Domain Nucleation and Growth in an Epitaxially Grown Wurtzite Ferroelectric
Ferroelectric domain nucleation and growth in epitaxial wurtzite (Al, B, Sc)N films are visualized through in situ transmission electron microscopy. Domains initiate near the bottom electrode and propagate laterally with zigzag walls, while unswitched regions remain near the electrode interfaces.
Sebastian Calderon +3 more
wiley +1 more source
The ARTEMIS project: Mixed-Signal IC for Edge-AI-based Classification of ECG Signals
Atrial fibrillation (AF) is a common heart arrhythmia and is closely associated with causing strokes. Diagnosis is usually performed with Holter monitors over longer periods of time, causing discomfort to the patient. The proposed mixed-signal integrated
Hoyer Ingo +7 more
doaj +1 more source
Design of a 1-chip IBM-3270 protocol handler [PDF]
The single-chip design of a 20MHz IBM-3270 coax protocol handler in a conventional 3 μ CMOS process-technology is discussed. The harmonious combination of CMOS circuit tricks and high-level design disciplines allows the 50k transistor design to be ...
Spaanenburg, L.
core +3 more sources
This work presents a novel sensing platform using metallo‐dielectric cryosoret nano‐assemblies and lossless photonic crystals to overcome limitations of conventional plasmonic biosensors. The hybrid system enhances both electric and magnetic field interactions, enabling amplified fluorescence, ultralow detection limits, and prism‐free, objective‐free ...
Seemesh Bhaskar +5 more
wiley +1 more source
This study addresses the demand for more efficient logic circuits by focusing on reducing area, power consumption, and delay. As conventional CMOS technology faces scaling and efficiency limitations, integrating emerging memory technologies like ...
NITHYA, N., PARAMASIVAM, K.
doaj +1 more source
Enabling Variability-Aware Design-Technology Co-Optimization for Advanced Memory Technologies
This paper presents a TCAD-based methodology to enable Design-Technology Co-Optimization (DTCO) of advanced semiconductor memories. After reviewing the DTCO approach to semiconductor devices scaling, we introduce a multi-stage simulation flow to study ...
Salvatore M. Amoroso +9 more
doaj +1 more source
CMOS realization of a 2-layer CNN universal machine chip [PDF]
Some of the features of the biological retina can be modelled by a cellular neural network (CNN) composed of two dynamically coupled layers of locally connected elementary nonlinear processors.
Carmona Galán, Ricardo +4 more
core +1 more source
The characteristics of a vertical n–p–i–p heterostructure transistor device, which exhibits a voltage‐tunable transition between Gaussian and sigmoid functions, are investigated. The mixed state of the transfer curve enables the utilization of both exploitation and exploration, improving computational performance in reinforcement learning tasks ...
Jisoo Park +7 more
wiley +1 more source
Design of a 90 GHz SOI Fin Electro-Optic Modulator for High-Speed Applications
Introducing high speed networks, such as the fifth generation of mobile technology and related applications including the internet of things, creates a pressing demand for hardware infrastructure that provides sufficient bandwidth.
Hany Mahrous +4 more
doaj +1 more source

