Results 231 to 240 of about 3,169,862 (288)

A tri-linear quantum dot architecture for semiconductor spin qubits. [PDF]

open access: yesSci Rep
Li R   +12 more
europepmc   +1 more source

Oxide Semiconductor Thin-Film Transistors for Low-Power Electronics. [PDF]

open access: yesAdv Sci (Weinh)
Ren S   +8 more
europepmc   +1 more source

A Study on Circuit Design of Integrated CMOS Analog Matched Filter

open access: yesA Study on Circuit Design of Integrated CMOS Analog Matched Filter
openaire   +1 more source
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Automatic biasing and sizing of CMOS analog integrated circuits

48th Midwest Symposium on Circuits and Systems, 2005., 2005
An automatic method is introduced to the biasing and sizing of CMOS analog ICs. First, from a netlist alike SPICE, a CMOS circuit is partitioned into sub-circuits by identifying current-loops formed by a group of transistors connected in a current bias path, beginning from the most positive voltage and finishing to the least negative one.
D. Torres-Munoz, E. Tielo-Cuautle
exaly   +2 more sources

CMOS analog integrated circuits based on weak inversion operations

IEEE Journal of Solid-State Circuits, 1977
A simple model describing the DC behavior of MOS transistors operating in weak inversion is derived on the basis of previous publications. This model includes only two parameters and is suitable for circuit design. It is verified experimentally for both p- and n-channel test transistors of a Si-gate low-voltage CMOS technology.
E. Vittoz, J. Fellrath
exaly   +2 more sources

Ultra-low Voltage Analog Integrated Circuits for nanoscale CMOS

Bipolar/BiCMOS Circuits and Technology Meeting, IEEE Proceedings of the, 2007
We will review design challenges and opportunities for ultra-low voltage analog and RF integrated circuits in nanoscale CMOS technologies.
Peter Kinget
exaly   +2 more sources

Design Consideration in High Temperature Analog CMOS Integrated Circuits

IEEE Transactions on Components, Hybrids and Manufacturing Technology, 1986
The design of CMOS analog integrated circuits to be operated at elevated junction temperatures is discussed. Considerations which have successfully been implemented in the design of basic analog cells for operation over the 25°-250°C range are emphasized.
exaly   +2 more sources

SiSMA—A Tool for Efficient Analysis of Analog CMOS Integrated Circuits Affected by Device Mismatch

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2004
In this paper a simulator for the statistical analysis of analog CMOS integrated circuits affected by technological tolerance effects, including device mismatch, is presented. The tool, able to perform dc, ac, and transient analyses, is based on a rigorous formulation of circuit equations starting from the modified nodal analysis and including random ...
Simone Orcioni   +2 more
exaly   +3 more sources

A simple noise modeling based testing of CMOS analog integrated circuits

SPIE Proceedings, 2005
A technique for testing CMOS analog integrated circuits is presented which is based on an analysis of the noise behavior of the circuit under test (CUT). The technique is simple and new. The CUT in the present work is an integrated CMOS amplifier circuit designed in a standard 1.5 μm n-well CMOS process for operation at ±;2.5 V.
Ashok Srivastava
exaly   +2 more sources

AMGIE : a Synthesis Environment for CMOS Analog Integrated Circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001
A synthesis environment for analog integrated circuits is presented that is able to drastically increase design and layout productivity for analog blocks. The system covers the complete design flow from specification over topology selection and optimal circuit sizing down to automatic layout generation and performance characterization.
Geert Van der Plas   +8 more
openaire   +4 more sources

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