Results 111 to 120 of about 769 (247)

Analogue techniques for very large scale integrated circuits

, 1992
The increased penetration of digital signal processing in integrated circuit (IC) technology has relegated analogue circuits to the role of interfacing with the analogue `outside world'.
Hughes, John Barry
core  

Fundamental Challenges, Physical Implementations, and Integration Strategies for Ising Machines in Large‐Scale Optimization Tasks

Advanced Electronic Materials, EarlyView.
Ising machines are emerging as specialized hardware solvers for computationally hard optimization problems. This review examines five major platforms—digital CMOS, analog CMOS, emerging devices, coherent optics, and quantum systems—highlighting physics‐rooted advantages and shared bottlenecks in scalability and connectivity.
Hyunjun Lee, Joon Pyo Kim, Sanghyeon Kim
wiley   +1 more source

MOOSE: A Physically Based Compact DC Model of SOI LDMOSFETs for Analogue Circuit Simulation

, 2004
In this paper, we present a compact model for silicon-on-insulator (SOI) laterally double diffused (LD) MOSFETs. The model is complete insofar as it uses no subcircuits, and is intended to predict device operation in all regions of bias.
Swanenberg, M., Mistry, K., Redman-White, W., Benson, J., D'Halleweyn, N.V.T.   +4 more
core  

Electrode‐Engineered Dual‐Mode Multifunctional Lead‐Free Perovskite Optoelectronic Memristors for Neuromorphic Computing

Advanced Electronic Materials, EarlyView.
A lead‐free perovskite memristive solar cell structure that call emulate both synaptic and neuronal functions controlled by light and electric fields depending on top electrode type. ABSTRACT Memristive devices based on halide perovskites hold strong promise to provide energy‐efficient systems for the Internet of Things (IoT); however, lead (Pb ...
Michalis Loizos, Konstantinos Rogdakis, Konstantinos Chatzimanolis, Katerina Anagnostou, Emmanuel Kymakis   +4 more
wiley   +1 more source

Model‐Based Time‐Modulated Write Algorithm for 1R Analog Memristive Crossbar Arrays

Advanced Electronic Materials, EarlyView.
A novel model‐based time‐modulated write algorithm efficiently programs analog 1R memristive crossbar arrays by varying pulse duration at a fixed voltage. By leveraging a physics‐based compact model and a dynamic gain mechanism, this approach overcomes device nonlinearities and parasitic effects.
Richard Schroedter, Ahmet Samil Demirkol, Ioannis Messaris, Christian Bruchatz, Eter Mgeladze, Stefan Slesazeck, Thomas Mikolajick, Ronald Tetzlaff   +7 more
wiley   +1 more source

A Compendium of Logic Gates Based on Reconfigurable Three‐Independent‐Gate Transistors Realized in FDSOI Hardware

Advanced Electronic Materials, EarlyView.
This work electrically characterizes sixteen logic gates built from three‐independent‐gate reconfigurable transistors fabricated on full‐scale 300 mm wafers using the industrial 22 nm fully depleted FDSOI process of GlobalFoundries. Static and time‐resolved measurements confirm correct operation, including a 1‐bit adder and reconfigurable AOI/OAI ...
Juan P. Martinez, Yuxuan He, Giulio Galderisi, Violetta Sessi, Niladri Bhattacharjee, Peter Baars, Kerstin Poenisch, Annekathrin Zeun, Konstantin Li, Fernando Koch, Binit Syamal, Thomas Mikolajick, Jens Trommer   +12 more
wiley   +1 more source

Emerging Memory and Device Technologies for Hardware‐Accelerated Model Training and Inference

Advanced Electronic Materials, EarlyView.
This review investigates the suitability of various emerging memory technologies as compute‐in‐memory hardware for artificial intelligence (AI) applications. Distinct requirements for training‐ and inference‐centric computing are discussed, spanning device physics, materials, and system integration.
Yoonho Cho, Dae‐won Kim, Yujin Kim, Jung‐Heum Na, Yuwon Jeong, Dong‐Yeop Lee, Shinhyun Choi   +6 more
wiley   +1 more source

A Rapid-prototyping CMOS-RRAM Integration Strategy. [PDF]

Microsyst Nanoeng
Tsiamis A, Stathopoulos S, Prodromakis T.   +2 more
europepmc   +1 more source

Yield Predictive Model Characterization in Analog Circuit Design [PDF]

, 2007
Brown, Andrew D, Sawal Hamid Md Ali, Wilson, Peter R, Andrew D. Brown, Ali, Sawal M, Peter R. Wilson   +5 more
core   +1 more source

Testing techniques and Fault Simulation for analogue CMOS integrated circuitsTitle

, 2001
As size and complexity of Integrated Circuits (ICs) keep increasing, testing those ICs is becoming more challenging task for test engineers. Time-to-Market (TtM) is perhaps the most important parameter in an IC's life cycle.
Kilic, Yavuz
core