Results 131 to 140 of about 557 (199)

A Memristor‐Based In‐Memory Computing System‐on‐Chip with Efficient Depthwise Convolution

Advanced Intelligent Systems, EarlyView.
We present a memristor‐based in‐memory computing (IMC) architecture that enables efficient depthwise convolution (DWC) acceleration. Fabricated in a system‐on‐chip with crossbar arrays, the design improves memory utilization. Experimental validation demonstrates the first hardware acceleration of DWC in IMC, achieving a digital comparable inference ...
Wenhao Song, Fuxi Cai, Sangsu Park, Zhaoyan Li, Seonghun Lee, Mingyi Rao, Woohyung Choi, Seungin Shin, Yan Zhu, Sujin Chae, Myoungsub Kim, Mingche Wu, Hyejung Choi, Yuan Dao, Jaeyun Yi, Youngman Cho, Seon Yong Cha, Ning Ge, Qiangfei Xia, Soo Gil Kim, Miao Hu, J. Joshua Yang   +21 more
wiley   +1 more source

An integrated large-scale photonic accelerator with ultralow latency. [PDF]

Nature
Hua S, Divita E, Yu S, Peng B, Roques-Carmes C, Su Z, Chen Z, Bai Y, Zou J, Zhu Y, Xu Y, Lu CK, Di Y, Chen H, Jiang L, Wang L, Ou L, Zhang C, Chen J, Zhang W, Zhu H, Kuang W, Wang L, Meng H, Steinman M, Shen Y.   +25 more
europepmc   +1 more source

Exploiting Ferroelectric and Spintronic Dynamics for Neural Network Computation

Advanced Intelligent Systems, EarlyView.
Ferroelectric and spintronic devices, relying on the control of polarization and magnetization, offer intrinsically fast, durable, energy‐efficient, and low‐latency building blocks for analog in‐memory computing. The hysteretic dynamics of an order parameter are leveraged to provide nonvolatile, multistate memory and nonlinear switching. Brain‐inspired
Dashiell Harrison, Kevin Nadaud, Josquin Harrison, Guillaume F. Nataf, Laura Bégon‐Lours   +4 more
wiley   +1 more source

In vivo microelectrode arrays for neuroscience. [PDF]

Nat Rev Methods Primers
Williams NP, Voroslakos M, Shi D, Pwint MY, Lanzio V, Mao H, Zolotavin P, Yoon E, Stieglitz T, Xie C, Harris TD, Schwartz AB, Cui XT.   +12 more
europepmc   +1 more source

Physics‐Grounded Probabilistic Bits for Hardware‐Efficient Intelligent Inference and Optimization

Advanced Intelligent Systems, EarlyView.
Si–SiNx interface traps are harnessed as a complementary metal–oxide–semiconductor‐compatible source of controllable randomness for probabilistic bits. Pulse‐width‐programmed stochastic capture converts nanoscale defect dynamics into Boltzmann‐consistent binary outputs, while a physics‐based Simulation Program with Integrated Circuit Emphasis model ...
Dokyoung Lee, Jun‐Young Park, Joon‐Kyu Han, Sungho Kim   +3 more
wiley   +1 more source

Miniaturisation of Raman spectroscopy systems: from benchtop to backpocket.

Lab Chip
Hardy M, Kanade PP, Buchan E, Goldberg Oppenheimer P, McPolin CPT, Bowman RM.   +5 more
europepmc   +1 more source

Actor-critic networks with analogue memristors mimicking reward-based learning. [PDF]

Nat Mach Intell
Portner K, Zellweger T, Martinelli F, Bégon-Lours L, Bragaglia V, Weilenmann C, Jubin D, Falcone DF, Hermann F, Hrynkevych O, Stecconi T, La Porta A, Drechsler U, Olziersky A, Offrein BJ, Gerstner W, Luisier M, Emboras A.   +17 more
europepmc   +1 more source

Energy‐Aware Perturbation Optimization for Memristor‐Array Convolutional Neural Networks

Advanced Intelligent Systems, EarlyView.
Memristor‐array inference becomes more energy efficient when layer inputs are reshaped before computation. Sinusoidal perturbation encoding with dual‐threshold screening reduces active voltage pulses and contracts ADC input‐current ranges, jointly lowering crossbar and peripheral energy while preserving accuracy across hardware MNIST validation, deep ...
Ao Xu, Lun Lu, Youpeng Wu, Yao Guo, Yi Li, Yinan Wang, Qingjiang Li   +6 more
wiley   +1 more source

Hardware implementation of memristor-based artificial neural networks. [PDF]

Nat Commun
Aguirre F, Sebastian A, Le Gallo M, Song W, Wang T, Yang JJ, Lu W, Chang MF, Ielmini D, Yang Y, Mehonic A, Kenyon A, Villena MA, Roldán JB, Wu Y, Hsu HH, Raghavan N, Suñé J, Miranda E, Eltawil A, Setti G, Smagulova K, Salama KN, Krestinskaya O, Yan X, Ang KW, Jain S, Li S, Alharbi O, Pazos S, Lanza M.   +30 more
europepmc   +1 more source

Single‐Step Analog In‐Memory Matrix Computation in Three‐Dimensional Circuits

Advanced Intelligent Systems, EarlyView.
A wooden model illustrates a 3D memristive array designed for single‐step kernel convolutions. It shows how two‐dimensional input data are mapped into the 3D array and convolved in parallel with stored kernels. Color‐coded connection points represent programmed memory‐element values, with each color corresponding to a specific kernel weight.
Alireza Jaberi Rad, Koushik Kumar, Fatemeh Kiani, Yi Huang, Ali Abdel‐Maksoud, Zheshun Xiong, Yunzhi Ling, Wuyu Zhao, Qiangfei Xia   +8 more
wiley   +1 more source