Low-Power Memristor for Neuromorphic Computing: From Materials to Applications. [PDF]
Nanomicro LettXia Z +5 more
europepmc +1 more source
International Journal of Circuit Theory and Applications, EarlyView.A ramp‐based phase‐locked loop (RPLL) active rectifier operating at 40.68 MHz compensates switching delay variations to improve phase alignment. The proposed architecture achieves 90.3% peak power conversion efficiency and 98.0% voltage conversion ratio for high‐frequency wireless power transfer in implantable medical devices.
Woorim Lee +5 more
wiley +1 more source
Multifunctional Organic Materials, Devices, and Mechanisms for Neuroscience, Neuromorphic Computing, and Bioelectronics. [PDF]
Nanomicro LettHoch FL, Wang Q, Lim KG, Loke DK.
europepmc +1 more source
Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization
International Journal of Circuit Theory and Applications, EarlyView.This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley +1 more source
Design of a Modularized IoT Multi-Functional Sensing System and Data Pipeline for Digital Twin-Oriented Real-Time Aircraft Structural Health Monitoring. [PDF]
Sensors (Basel)Guo S +4 more
europepmc +1 more source
Parallel Multi‐Operand Addition Using CPA‐Trees and Carry‐Select Adders
International Journal of Circuit Theory and Applications, EarlyView.A balanced parallel CPA‐tree architecture with CSLA reduces the critical‐path delay of multi‐operand addition while preserving structural regularity. ASIC results demonstrate delay reductions of up to 34% with low area overhead, providing an efficient and scalable solution for high‐performance arithmetic.
Lucas R. Kieslich +3 more
wiley +1 more source
CMOS plus stochastic nanomagnets enabling heterogeneous computers for probabilistic inference and learning. [PDF]
Nat CommunSingh NS +10 more
europepmc +1 more source
An Ultra‐Low‐Power Biopotential Acquisition Analog Front‐End Chip for Wearable Devices
International Journal of Circuit Theory and Applications, EarlyView.A 0.8‐V, 1.2‐μW biopotential AFE combines a chopper‐stabilized CCIA with dual‐time‐scale EDO management. The slow DSL preserves > 1 GΩ input impedance, whereas an event‐triggered fast‐recovery path shortens return to the linear range after abrupt electrode‐offset disturbances. ABSTRACT A 0.8‐V, 1.2‐μW biopotential analog front‐end (AFE) IC is presented
Zhang Xin +4 more
wiley +1 more source
Memristive ternary Łukasiewicz logic based on reading-based ratioed resistive states (3R). [PDF]
Philos Trans A Math Phys Eng SciLiu F +5 more
europepmc +1 more source
A Code‐Invariant QSG–VGA Co‐Design Methodology for Compact CMOS Vector‐Sum Phase Shifters
International Journal of Circuit Theory and Applications, EarlyView.A circuit‐level co‐design methodology for compact vector‐sum phase shifters is presented, combining a code‐invariant common‐gate variable‐gain amplifier (VGA) with a resistorless quadrature signal generator (QSG). By maintaining an almost constant input resistance, explicit resistors are eliminated from the QSG.
Uxua Esteban Eraso +4 more
wiley +1 more source